GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs
ID
817660
Date
4/07/2025
Public
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1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP
4. Implementing the GTS System PLL Clocks Intel FPGA IP
5. Implementing the GTS Reset Sequencer Intel FPGA IP
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs
3.1. IP Overview
3.2. Designing with the GTS PMA/FEC Direct PHY Intel FPGA IP
3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP
3.4. Reconfigurable PHY
3.5. Signal and Port Reference
3.6. Bit Mapping for PMA, FEC, and PCS Mode PHY TX and RX Datapath
3.7. Clocking
3.8. Custom Cadence Generation Ports and Logic
3.9. Asserting Reset
3.10. Bonding Implementation
3.11. Configuration Register
3.12. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing
3.13. Configurable Quartus® Prime Software Settings
3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.3.1. Preset IP Parameter Settings
3.3.2. Mode and Common Datapath Options
3.3.3. Reconfigurable PHY Settings
3.3.4. TX Datapath Options
3.3.5. RX Datapath Options
3.3.6. PMA Configuration Rules for Specific Protocol Mode Implementations
3.3.7. FEC Options
3.3.8. PCS Options
3.3.9. Avalon® Memory-Mapped Interface Options
3.3.10. Register Map IP-XACT Support
3.3.11. Analog Parameter Options
3.5.1. TX and RX Parallel and Serial Interface Signals
3.5.2. TX and RX Reference Clock and Clock Output Interface Signals
3.5.3. Reset Signals
3.5.4. FEC Signals
3.5.5. Custom Cadence Control and Status Signals
3.5.6. RX PMA Status Signals
3.5.7. TX and RX PMA and Core Interface FIFO Signals
3.5.8. Avalon Memory-Mapped Interface Signals
3.9.1. Reset Signal Requirements
3.9.2. Power On Reset Requirements
3.9.3. Reset Signals—Block Level
3.9.4. Run-time Reset Sequence—TX
3.9.5. Run-time Reset Sequence—RX
3.9.6. Run-time Reset Sequence—TX + RX
3.9.7. RX Data Loss/CDR Lock Loss (Auto-Recovery)
3.9.8. TX PLL Lock Loss
3.9.9. TX PLL Lock Loss Auto-Recovery (Soft CSR Enabled)
5.1. IP Requirements
5.2. IP Parameters
5.3. IP Port List
5.4. GTS Reset Sequencer Intel FPGA IP General Interface
5.5. GTS Reset Sequencer Intel FPGA IP Design Flow
5.6. GTS Reset Sequencer Intel FPGA IP Use Cases
5.7. Connecting the Reference Clock Buffer Status to the GTS Reset Sequencer Intel® FPGA IP
6.1. Instantiating the GTS PMA/FEC Direct PHY Intel FPGA IP
6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.3. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Functional Description
6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench
6.5. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.6. Hardware Testing the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.7. GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design
6.8. Generating the GTS PMA/FEC Direct PHY Intel® FPGA IP Reconfigurable Example Design
6.9. GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design Functional Description
6.10. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design Testbench
6.11. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design
6.12. Hardware Testing the GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design
6.8. Generating the GTS PMA/FEC Direct PHY Intel® FPGA IP Reconfigurable Example Design
To generate a reconfigurable example design, follow the steps below:
- For the Direct PHY Operation Mode parameter in the Mode settings, select the Reconfigurable PHY option.
- Navigate to the Example Design section towards the end of the GTS PMA/FEC Direct PHY Intel® FPGA IP GUI. From the Example Design Options drop-down menu, select one of the Reconfigurable PHY example design options that start with MRIP.
- Click the Acknowledgement option box. This option is to remind you that only the example design you specify in the drop-down menu is generated. If you make any modification to the parameter settings of the IP after selecting the Example Design options from the drop-down list, the changes you make to the IP parameters do not take effect. Only the parameters defined for the Example Design options in Example Design Options for the Reconfigurable PHY table take effect. If you do not check the acknowledgment box, you cannot generate the example design.
- If you are using the Agilex™ 5 FPGA premium development kit, you can select the board Intel Agilex™ 5 FPGA E-Series 065B Premium Development Kit (ES1) in the drop-down list. With this selection, the Quartus® Prime Pro Edition software generates the example design with the reference clock and channel pin assignments in the .qsf file.
- Ensure steps 3 and step 4 are done, then click Generate Example Design. Clicking Generate Example Design completes the IP Generation. An example design folder is generated containing the Quartus® Prime software project (.qpf), settings (.qsf), and IP files.
- In addition, there are two folders created named rtl and testbench containing the RTL and simulation testbench files in the following location:
<Project Folder>/<directphy_example_design/example_design>