GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs

ID 817660
Date 4/07/2025
Public

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6.8. Generating the GTS PMA/FEC Direct PHY Intel® FPGA IP Reconfigurable Example Design

To generate a reconfigurable example design, follow the steps below:
  1. For the Direct PHY Operation Mode parameter in the Mode settings, select the Reconfigurable PHY option.
  2. Navigate to the Example Design section towards the end of the GTS PMA/FEC Direct PHY Intel® FPGA IP GUI. From the Example Design Options drop-down menu, select one of the Reconfigurable PHY example design options that start with MRIP.
  3. Click the Acknowledgement option box. This option is to remind you that only the example design you specify in the drop-down menu is generated. If you make any modification to the parameter settings of the IP after selecting the Example Design options from the drop-down list, the changes you make to the IP parameters do not take effect. Only the parameters defined for the Example Design options in Example Design Options for the Reconfigurable PHY table take effect. If you do not check the acknowledgment box, you cannot generate the example design.
  4. If you are using the Agilex™ 5 FPGA premium development kit, you can select the board Intel Agilex™ 5 FPGA E-Series 065B Premium Development Kit (ES1) in the drop-down list. With this selection, the Quartus® Prime Pro Edition software generates the example design with the reference clock and channel pin assignments in the .qsf file.
  5. Ensure steps 3 and step 4 are done, then click Generate Example Design. Clicking Generate Example Design completes the IP Generation. An example design folder is generated containing the Quartus® Prime software project (.qpf), settings (.qsf), and IP files.
  6. In addition, there are two folders created named rtl and testbench containing the RTL and simulation testbench files in the following location:
    <Project Folder>/<directphy_example_design/example_design>