GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs

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Date 4/07/2025
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Document Table of Contents
Document Table of Contents x
1. GTS Transceiver Overview 2. GTS Transceiver Architecture 3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP 4. Implementing the GTS System PLL Clocks Intel FPGA IP 5. Implementing the GTS Reset Sequencer Intel FPGA IP 6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design 7. Design Assistance Tools 8. Debugging GTS Transceiver Links with Transceiver Toolkit 9. Document Revision History for the GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs
1. GTS Transceiver Overview x
1.1. GTS Transceiver Design Flow
2. GTS Transceiver Architecture x
2.1. Building Blocks 2.2. Channel Placement Rules and Design Requirements 2.3. PMA Architecture 2.4. PCS Architecture 2.5. Forward Error Correction (FEC) Architecture 2.6. Clock Architecture 2.7. Bonding and Deskew
2.1. Building Blocks x
2.1.1. PMA 2.1.2. FEC 2.1.3. PCS 2.1.4. Ethernet MAC 2.1.5. PCI Express* Hard IP 2.1.6. PLL and Clock Networks 2.1.7. Avalon® Memory-Mapped Interface
2.1.1. PMA x
2.1.1.1. Protocol Support Using PMA Direct Mode
2.1.1.1. Protocol Support Using PMA Direct Mode x
2.1.1.1.1. SDI 2.1.1.1.2. HDMI 2.1.1.1.3. CPRI 2.1.1.1.4. GPON
2.2. Channel Placement Rules and Design Requirements x
2.2.1. Hard IP Rules 2.2.2. Use Scenario Rules 2.2.3. Unused PMA Rules 2.2.4. General Design Requirement
2.2.3. Unused PMA Rules x
2.2.3.1. Unused PMA Not Planned for Use in the Future 2.2.3.2. Unused PMA Planned for Use in the Future
2.3. PMA Architecture x
2.3.1. Transmitter PMA Architecture 2.3.2. Receiver PMA Architecture 2.3.3. PMA Loopback Modes
2.3.1. Transmitter PMA Architecture x
2.3.1.1. Transmitter Buffer 2.3.1.2. Serializer 2.3.1.3. Data Pattern Generator and Verifier
2.3.2. Receiver PMA Architecture x
2.3.2.1. Receiver Buffer and Equalizer 2.3.2.2. Deserializer 2.3.2.3. CDR Block 2.3.2.4. PMA Tuning
2.3.2.1. Receiver Buffer and Equalizer x
2.3.2.1.1. Control Unit
2.5. Forward Error Correction (FEC) Architecture x
2.5.1. FEC Loopback Mode
2.6. Clock Architecture x
2.6.1. Reference Clock Network 2.6.2. Datapath Clock Network 2.6.3. System PLL 2.6.4. Datapath Clock Cadences 2.6.5. Shared Clocking Resources Between the GTS Transceiver Bank and HVIO Bank
2.6.1. Reference Clock Network x
2.6.1.1. Single GTS Transceiver Bank Device 2.6.1.2. PMA Primary PLL Configuration
2.6.3. System PLL x
2.6.3.1. I/O PLLs in HVIO Bank as System PLL 2.6.3.2. Running PCIe* and Non- PCIe* Protocols in a GTS Transceiver Bank 2.6.3.3. System PLL Clock for FPGA Core 2.6.3.4. System PLL with HVIO Reference Clock
2.7. Bonding and Deskew x
2.7.1. Bonding Architecture 2.7.2. TX Deskew Function
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP x
3.1. IP Overview 3.2. Designing with the GTS PMA/FEC Direct PHY Intel FPGA IP 3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP 3.4. Reconfigurable PHY 3.5. Signal and Port Reference 3.6. Bit Mapping for PMA, FEC, and PCS Mode PHY TX and RX Datapath 3.7. Clocking 3.8. Custom Cadence Generation Ports and Logic 3.9. Asserting Reset 3.10. Bonding Implementation 3.11. Configuration Register 3.12. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing 3.13. Configurable Quartus® Prime Software Settings 3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.1. IP Overview x
3.1.1. PMA Direct Supported Modes 3.1.2. FEC Direct Supported Modes 3.1.3. PCS Direct Supported Modes 3.1.4. Unsupported PMA/FEC/PCS Modes
3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP x
3.3.1. Preset IP Parameter Settings 3.3.2. Mode and Common Datapath Options 3.3.3. Reconfigurable PHY Settings 3.3.4. TX Datapath Options 3.3.5. RX Datapath Options 3.3.6. PMA Configuration Rules for Specific Protocol Mode Implementations 3.3.7. FEC Options 3.3.8. PCS Options 3.3.9. Avalon® Memory-Mapped Interface Options 3.3.10. Register Map IP-XACT Support 3.3.11. Analog Parameter Options
3.3.4. TX Datapath Options x
3.3.4.1. TX PMA Interface Parameters
3.3.5. RX Datapath Options x
3.3.5.1. RX PMA Interface Parameters
3.3.6. PMA Configuration Rules for Specific Protocol Mode Implementations x
3.3.6.1. PMA Configuration Rules for SDI Mode 3.3.6.2. PMA Configuration Rules for HDMI Mode 3.3.6.3. PMA Configuration Rules for CPRI Mode 3.3.6.4. PMA Configuration Rules for GPON Mode
3.4. Reconfigurable PHY x
3.4.1. Clock Generation and Constraints for Multiple Profiles Design
3.5. Signal and Port Reference x
3.5.1. TX and RX Parallel and Serial Interface Signals 3.5.2. TX and RX Reference Clock and Clock Output Interface Signals 3.5.3. Reset Signals 3.5.4. FEC Signals 3.5.5. Custom Cadence Control and Status Signals 3.5.6. RX PMA Status Signals 3.5.7. TX and RX PMA and Core Interface FIFO Signals 3.5.8. Avalon Memory-Mapped Interface Signals
3.7. Clocking x
3.7.1. Clock Ports 3.7.2. Recommended tx/rx_coreclkin Connection and tx/rx_clkout2 Source 3.7.3. Port Widths and Recommended Connections for tx/rx_coreclkin, tx/rx_clkout, and tx/rx_clkout2 3.7.4. PMA Fractional Mode 3.7.5. Input Reference Clock Buffer Protection
3.7.5. Input Reference Clock Buffer Protection x
3.7.5.1. Reference Clock Buffer Register Information 3.7.5.2. Re-enabling the Reference Clock Buffers
3.8. Custom Cadence Generation Ports and Logic x
3.8.1. Enabling the i_tx_cadence_slow_clk_locked Port
3.9. Asserting Reset x
3.9.1. Reset Signal Requirements 3.9.2. Power On Reset Requirements 3.9.3. Reset Signals—Block Level 3.9.4. Run-time Reset Sequence—TX 3.9.5. Run-time Reset Sequence—RX 3.9.6. Run-time Reset Sequence—TX + RX 3.9.7. RX Data Loss/CDR Lock Loss (Auto-Recovery) 3.9.8. TX PLL Lock Loss 3.9.9. TX PLL Lock Loss Auto-Recovery (Soft CSR Enabled)
3.10. Bonding Implementation x
3.10.1. Bonding Placement Requirements 3.10.2. Multilane RX Simplex Implementation
3.11. Configuration Register x
3.11.1. GTS PMA and FEC Direct PHY Soft CSR Register Map 3.11.2. GTS PMA Register Map 3.11.3. Accessing Configuration Registers 3.11.4. Configuration Registers for the GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY
3.11.2. GTS PMA Register Map x
3.11.2.1. Logical Avalon® Memory-Mapped Port Indexing
3.11.3. Accessing Configuration Registers x
3.11.3.1. Accessing GTS PMA and FEC Direct PHY Soft CSR Registers 3.11.3.2. Accessing GTS PMA Registers
3.12. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing x
3.12.1. Using Debug Endpoint Interface within the GTS PMA/FEC Direct PHY Intel FPGA IP 3.12.2. Using JTAG to Avalon Master Bridge Intel FPGA IP
3.12.1. Using Debug Endpoint Interface within the GTS PMA/FEC Direct PHY Intel FPGA IP x
3.12.1.1. RTL Connection Example for Debug Endpoint Avalon® Interface
3.12.2. Using JTAG to Avalon Master Bridge Intel FPGA IP x
3.12.2.1. RTL Connection Example for JTAG to Avalon Master Bridge Intel® FPGA IP
3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface x
3.14.1. Direct Register Method 3.14.2. GTS Attribute Access Method
3.14.1. Direct Register Method x
3.14.1.1. Direct Register Method Examples
3.14.2. GTS Attribute Access Method x
3.14.2.1. GTS Attribute Access Method Example 1 3.14.2.2. GTS Attribute Access Method Example 2 3.14.2.3. GTS Attribute Access Method Example 3
4. Implementing the GTS System PLL Clocks Intel FPGA IP x
4.1. IP Parameters 4.2. IP Port List 4.3. Mode of System PLL - System PLL Reference Clock and Output Frequencies 4.4. Guidelines for GTS System PLL Clocks Intel FPGA IP Usage 4.5. Guidelines to Indicate System PLL Reference Clock is Ready
4.5. Guidelines to Indicate System PLL Reference Clock is Ready x
4.5.1. Example Flow to Indicate System PLL Reference Clock is Ready
5. Implementing the GTS Reset Sequencer Intel FPGA IP x
5.1. IP Requirements 5.2. IP Parameters 5.3. IP Port List 5.4. GTS Reset Sequencer Intel FPGA IP General Interface 5.5. GTS Reset Sequencer Intel FPGA IP Design Flow 5.6. GTS Reset Sequencer Intel FPGA IP Use Cases 5.7. Connecting the Reference Clock Buffer Status to the GTS Reset Sequencer Intel® FPGA IP
5.6. GTS Reset Sequencer Intel FPGA IP Use Cases x
5.6.1. Example Use Case 1 5.6.2. Example Use Case 2
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design x
6.1. Instantiating the GTS PMA/FEC Direct PHY Intel FPGA IP 6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design 6.3. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Functional Description 6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench 6.5. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design 6.6. Hardware Testing the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design 6.7. GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design 6.8. Generating the GTS PMA/FEC Direct PHY Intel® FPGA IP Reconfigurable Example Design 6.9. GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design Functional Description 6.10. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design Testbench 6.11. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design 6.12. Hardware Testing the GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design
6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design x
6.2.1. Fast Simulation Support 6.2.2. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Directory Structure
6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench x
6.4.1. Modifying the Example Design and Performing Simulation
6.8. Generating the GTS PMA/FEC Direct PHY Intel® FPGA IP Reconfigurable Example Design x
6.8.1. Fast Simulation Support 6.8.2. GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design Directory Structure
7. Design Assistance Tools x
7.1. Clocking and Datapath Tool 7.2. TX Equalizer Tool
8. Debugging GTS Transceiver Links with Transceiver Toolkit x
8.1. GTS Transceiver Toolkit Parameter Settings 8.2. GTS Transceiver Toolkit GUI 8.3. GTS Transceiver Debugging Flow Walkthrough
8.2. GTS Transceiver Toolkit GUI x
8.2.1. Collection View
8.3. GTS Transceiver Debugging Flow Walkthrough x
8.3.1. Modifying the Design to Enable GTS Transceiver Debug Toolkit 8.3.2. Programming the Design into an Intel FPGA 8.3.3. Loading the Design to the Transceiver Toolkit 8.3.4. Creating Transceiver Links 8.3.5. Running BER Tests 8.3.6. Running Eye Viewer Tests 8.3.7. Running Link Optimization Tests
1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP
4. Implementing the GTS System PLL Clocks Intel FPGA IP
5. Implementing the GTS Reset Sequencer Intel FPGA IP
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs

3.14.2. GTS Attribute Access Method

Using the GTS attribute access method, you update the GTS PMA registers to configure hardware with a specific sequence of commands.
For example, you can configure serial internal loopback, TX and RX polarity inversion using the GTS attribute access method. The GTS attribute access method consists of 4 steps in a sequence as shown below:
  1. Write a data value to the LINK_MNG_SIDE_CPI_REGS register to assert a service request.
  2. Read the PHY_SIDE_CPI_REGS register to confirm the request has been acknowledged and completed; if not, repeat this step.
  3. Write a data value to the LINK_MNG_SIDE_CPI_REGS register to deassert the service request.
  4. Read the PHY_SIDE_CPI_REGS register to confirm the request in step 3 has been acknowledged; if not, repeat this step.
Table 74.  GTS Attribute Access Addresses for JTAG Master that Controls 8 Channels (Enable separate Avalon interface per PMA = OFF)
Channels LINK_MNG_SIDE_CPI_REGS Address PHY_SIDE_CPI_REGS Address
Channel 0 0x000A403C 0x000A4040
Channel 1 0x001A403C 0x001A4040
Channel 2 0x002A403C 0x002A4040
Channel 3 0x003A403C 0x003A4040
Channel 4 0x004A403C 0x004A4040
Channel 5 0x005A403C 0x005A4040
Channel 6 0x006A403C 0x006A4040
Channel 7 0x007A403C 0x007A4040
Table 75.  GTS Attribute Access Data Value 1
  Loopback Mode TX and RX PRBS Selection Polarity Setup 41 BER Measurement Start/Stop Test
Data field[31:16]

Enable serial loopback: 0x6

Enable TX to RX parallel loopback: 0x4

Enable RX to TX parallel loopback: 0x3

Disable loopback: 0x0

PRBS7: 0x208

PRBS9: 0x249

PRBS13: 0x965

PRBS15: 0xA69

PRBS23: 0x2CB

PRBS31: 0x30C

Reverse: 0x1

Revert back: 0x0

 0x14

Start: 0x20

Stop: 0x21
Option field [15:12]

Bit [15] SERVICE_REQ to indicate a request: 0 = no request, 1 = service requested.

Bit [14] RESET: 0 = not in reset, 1 = in reset.

Bit [13] SET_GET: 0 = GET parameters, 1 = SET parameters.

Bit [12]: reserved
Lane number field[11:8] Use 0xA5000[1:0], 0x1A5000[1:0]… 0x7A5000 [1:0] to read back logical lane 0, 1 until lane 7 ’s physical lane number.
  • If return value is 2’b00, physical lane is 0
  • If return value is 2’b01, physical lane is 1
  • If return value is 2’b10, physical lane is 2
  • If return value is 2’b11, physical lane is 3
Opcode field[7:0] 0x40 0x41

TX polarity: 0x65

RX polarity: 0x66

 0x45 0x0F
Note: 0x0F is not equivalent to 0xF
Table 76.  GTS Attribute Access Data Value 2
  Get Status Error Number to Inject Enable Error Injection Read Results Finish BER Measurement
Data field[31:16]

0x0

0x[Error_Num]

0x23

0x0

0x0
Option field [15:12]

Bit [15] SERVICE_REQ to indicate a request: 0 = no request, 1 = service requested.

Bit [14] RESET: 0 = not in reset, 1 = in reset.

Bit [13] SET_GET: 0 = GET parameters, 1 = SET parameters.

Bit [12]: reserved
Lane number field[11:8] Use 0xA5000[1:0], 0x1A5000[1:0]… 0x7A5000 [1:0] to read back logical lane 0, 1 until lane 7 ’s physical lane number.
  • If return value is 2’b00, physical lane is 0
  • If return value is 2’b01, physical lane is 1
  • If return value is 2’b10, physical lane is 2
  • If return value is 2’b11, physical lane is 3
Opcode field[7:0] 0x49: Get Test status

0x0D: Get PMA status

 0x42 0x0F
Note: 0x0F is not equivalent to 0xF
  • LSB: 0x4A
  • Middle: 0x4B
  • MSB: 0x4C
 0x41
Table 77.  GTS Attribute Access Data Value 3
  RX CDR Clock
Data field[31:16]

Bit [31:30]: Lane ID to use as source for rx_cdr_divclk_link0

Bit [29]:

1'b1: Enable rx_cdr_divclk_link0

1'b0: Disable rx_cdr_divclk_link0

Bit [28:25]: Read only for GET command to return the lane ID source

0x0: rx_cdr_divclk_link0 is enabled with lane 0 as source

0x1: rx_cdr_divclk_link0 is enabled with lane 1 as source

0x2: rx_cdr_divclk_link0 is enabled with lane 2 as source

0x3: rx_cdr_divclk_link0 is enabled with lane 3 as source

0xF: rx_cdr_divclk_link0 is disabled

Bit [24:16]: Reserved
Option field[15:12]

Bit [15] SERVICE_REQ to indicate a request: 0 = no request, 1 = service requested.

Bit [14] RESET: 0 = not in reset, 1 = in reset.

Bit [13] SET_GET: 0 = GET parameters, 1 = SET parameters.

Bit [12]: reserved
Lane number field[11:8] Use 0xA5000[1:0], 0x1A5000[1:0]… 0x7A5000 [1:0] to read back logical lane 0, 1 until lane 7 ’s physical lane number.
  • If return value is 2’b00, physical lane is 0
  • If return value is 2’b01, physical lane is 1
  • If return value is 2’b10, physical lane is 2
  • If return value is 2’b11, physical lane is 3
Opcode field[7:0] 0xB1
You can create a function to write data, or read to and from GTS attribute access addresses. The data is comprised of data field[31:16], option field[15:12], lane number field[11:8], and opcode field[7:0]. The following examples use the tcl process as shown below: 
proc attribute_access {{data field} {option field} {lane number field} {opcode field}}
You can use any programming language to perform the read and writes. For the other GTS PMA lanes, refer to GTS Attribute Access Addresses for JTAG Master that Controls 8 channels for LINK_MNG_SIDE_CPI_REGS and PHY_SIDE_CPI_REGS, and refer to GTS Attribute Access Data Value 1 for lane number field information.

Section Content
GTS Attribute Access Method Example 1
GTS Attribute Access Method Example 2
GTS Attribute Access Method Example 3

41 This feature support is preliminarily and not supported in hardware in the current Quartus® Prime Pro Edition software release.
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