GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs

ID 817660
Date 4/07/2025
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.3.3. Reconfigurable PHY Settings

Figure 41. Reconfigurable PHY Settings in Parameter Editor

When you generate the GTS PMA/FEC Direct PHY Intel® FPGA IP in the Reconfigurable PHY mode, you cannot directly instantiate it into your design in the Quartus® Prime Pro Edition software. Refer to the additional steps outlined in the GTS Dynamic Reconfiguration Controller IP User Guide and the GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design section of this document.

Table 24.  Common Settings Reconfigurable PHY Parameters
Parameter Values Description
Reconfigurable group 1 lane

Sets reconfiguration group by selecting number of lanes that needs to be reconfigured. Only 1 lane is supported in the current Quartus® Prime Pro Edition software release.

Default value is 1 lane.

PMA mode

Duplex,

TX Simplex,

RX Simplex

Selects the transceiver operation mode.

Default value is Duplex

Enable FEC use On/Off

Enables the FEC option for all reconfigurable DPHY profiles. When this option is enabled, FEC for each profile can be individually enabled or disabled in the FEC tab and configured with the required FEC option for that specific profile.

Default value is Off

System PLL Frequency 32.5 to 1000 MHz

Specifies the system PLL clock frequency (MHz) and is applicable if Datapath clocking mode is selected as system PLL.

Default value is 322.265625 MHz

Note: You must ensure that the system PLL frequency and GTS System PLL Clocks Intel FPGA IP frequency is set to the same value if you are using the system PLL clocking mode.

Number of Secondary profiles 1 - 11

Specifies the total number of secondary profiles.

Default value is 1.