GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs

ID 817660
Date 4/07/2025
Public

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6.9. GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design Functional Description

The GTS PMA/FEC Direct PHY Intel® FPGA IP Reconfigurable PHY example design simulation testbench top-level block diagram is shown in the following figure.
Figure 95. Simulation Testbench Block Diagram for the Reconfigurable PHY 2 Profile MRIP Example Design

This section provides the functional description of the example design for the two profile MRIP 1 x 10.3125G PMA Direct(P0) to FEC Direct Mode(P1) (System PLL Clocking) example design. In this design, you can dynamically reconfigure the IP between the PMA direct mode and the FEC direct mode.

The GTS PMA/FEC Direct PHY Intel® FPGA IP Reconfigurable PHY example design includes the following components:
  • GTS PMA/FEC Direct PHY Intel® FPGA IP : Generated Reconfigurable PHY IP core.
  • GTS Dynamic Reconfiguration Controller Intel® FPGA IP : Instantiated Dynamic Reconfiguration (DR) controller IP. The GTS Dynamic Reconfiguration Controller Intel® FPGA IP parameter editor settings align with the transceiver channels, supported profiles, and CSR clock frequency in the GTS PMA/FEC Direct PHY Intel® FPGA IP. If you generate the example design using the Generate Example Design button in the IP parameter editor, the IP instantiates automatically. If you create your own design example, you must manually instantiate this IP and connect all the I/O ports.
  • GTS System PLL Clocks Intel® FPGA IP : Instantiated System PLL Clocks IP. The GTS System PLL Clocks Intel® FPGA IP parameter editor settings align with the system PLL frequency in the GTS PMA/FEC Direct PHY Intel® FPGA IP. If you generate the design example using the Generate Example Design button in the IP parameter editor, the IP instantiates automatically. If you create your own example design, you must manually instantiate this IP and connect all the I/O ports.
  • GTS Reset Sequencer Intel® FPGA IP : Instantiated Reset Sequencer IP. If you generate the design example using the Generate Example Design button in the IP parameter editor, the IP instantiates automatically. If you create your own example design, you must manually instantiate this IP and connect all the I/O ports.

The example design is configured with a 100 MHz clock for reconfiguration, a 156.25 MHz reference clock for the system PLL, and a 156.25 MHz clock for the GTS PMA direct channel, which is used as both the TX PLL and the RX CDR reference clock.

Refer to the GTS Dynamic Reconfiguration Controller Intel® FPGA IP for details about custom design steps.