GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs
ID
817660
Date
4/07/2025
Public
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1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP
4. Implementing the GTS System PLL Clocks Intel FPGA IP
5. Implementing the GTS Reset Sequencer Intel FPGA IP
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs
3.1. IP Overview
3.2. Designing with the GTS PMA/FEC Direct PHY Intel FPGA IP
3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP
3.4. Reconfigurable PHY
3.5. Signal and Port Reference
3.6. Bit Mapping for PMA, FEC, and PCS Mode PHY TX and RX Datapath
3.7. Clocking
3.8. Custom Cadence Generation Ports and Logic
3.9. Asserting Reset
3.10. Bonding Implementation
3.11. Configuration Register
3.12. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing
3.13. Configurable Quartus® Prime Software Settings
3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.3.1. Preset IP Parameter Settings
3.3.2. Mode and Common Datapath Options
3.3.3. Reconfigurable PHY Settings
3.3.4. TX Datapath Options
3.3.5. RX Datapath Options
3.3.6. PMA Configuration Rules for Specific Protocol Mode Implementations
3.3.7. FEC Options
3.3.8. PCS Options
3.3.9. Avalon® Memory-Mapped Interface Options
3.3.10. Register Map IP-XACT Support
3.3.11. Analog Parameter Options
3.5.1. TX and RX Parallel and Serial Interface Signals
3.5.2. TX and RX Reference Clock and Clock Output Interface Signals
3.5.3. Reset Signals
3.5.4. FEC Signals
3.5.5. Custom Cadence Control and Status Signals
3.5.6. RX PMA Status Signals
3.5.7. TX and RX PMA and Core Interface FIFO Signals
3.5.8. Avalon Memory-Mapped Interface Signals
3.9.1. Reset Signal Requirements
3.9.2. Power On Reset Requirements
3.9.3. Reset Signals—Block Level
3.9.4. Run-time Reset Sequence—TX
3.9.5. Run-time Reset Sequence—RX
3.9.6. Run-time Reset Sequence—TX + RX
3.9.7. RX Data Loss/CDR Lock Loss (Auto-Recovery)
3.9.8. TX PLL Lock Loss
3.9.9. TX PLL Lock Loss Auto-Recovery (Soft CSR Enabled)
5.1. IP Requirements
5.2. IP Parameters
5.3. IP Port List
5.4. GTS Reset Sequencer Intel FPGA IP General Interface
5.5. GTS Reset Sequencer Intel FPGA IP Design Flow
5.6. GTS Reset Sequencer Intel FPGA IP Use Cases
5.7. Connecting the Reference Clock Buffer Status to the GTS Reset Sequencer Intel® FPGA IP
6.1. Instantiating the GTS PMA/FEC Direct PHY Intel FPGA IP
6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.3. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Functional Description
6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench
6.5. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.6. Hardware Testing the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.7. GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design
6.8. Generating the GTS PMA/FEC Direct PHY Intel® FPGA IP Reconfigurable Example Design
6.9. GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design Functional Description
6.10. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design Testbench
6.11. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design
6.12. Hardware Testing the GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design
6.9. GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design Functional Description
The GTS PMA/FEC Direct PHY Intel® FPGA IP Reconfigurable PHY example design simulation testbench top-level block diagram is shown in the following figure.
Figure 95. Simulation Testbench Block Diagram for the Reconfigurable PHY 2 Profile MRIP Example Design
This section provides the functional description of the example design for the two profile MRIP 1 x 10.3125G PMA Direct(P0) to FEC Direct Mode(P1) (System PLL Clocking) example design. In this design, you can dynamically reconfigure the IP between the PMA direct mode and the FEC direct mode.
The GTS PMA/FEC Direct PHY Intel® FPGA IP Reconfigurable PHY example design includes the following components:
- GTS PMA/FEC Direct PHY Intel® FPGA IP : Generated Reconfigurable PHY IP core.
- GTS Dynamic Reconfiguration Controller Intel® FPGA IP : Instantiated Dynamic Reconfiguration (DR) controller IP. The GTS Dynamic Reconfiguration Controller Intel® FPGA IP parameter editor settings align with the transceiver channels, supported profiles, and CSR clock frequency in the GTS PMA/FEC Direct PHY Intel® FPGA IP. If you generate the example design using the Generate Example Design button in the IP parameter editor, the IP instantiates automatically. If you create your own design example, you must manually instantiate this IP and connect all the I/O ports.
- GTS System PLL Clocks Intel® FPGA IP : Instantiated System PLL Clocks IP. The GTS System PLL Clocks Intel® FPGA IP parameter editor settings align with the system PLL frequency in the GTS PMA/FEC Direct PHY Intel® FPGA IP. If you generate the design example using the Generate Example Design button in the IP parameter editor, the IP instantiates automatically. If you create your own example design, you must manually instantiate this IP and connect all the I/O ports.
- GTS Reset Sequencer Intel® FPGA IP : Instantiated Reset Sequencer IP. If you generate the design example using the Generate Example Design button in the IP parameter editor, the IP instantiates automatically. If you create your own example design, you must manually instantiate this IP and connect all the I/O ports.
The example design is configured with a 100 MHz clock for reconfiguration, a 156.25 MHz reference clock for the system PLL, and a 156.25 MHz clock for the GTS PMA direct channel, which is used as both the TX PLL and the RX CDR reference clock.
Refer to the GTS Dynamic Reconfiguration Controller Intel® FPGA IP for details about custom design steps.
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