GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs

ID 817660
Date 4/07/2025
Public

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3.4. Reconfigurable PHY

The Reconfigurable PHY allows you to configure multiple profile settings through the graphical user interface (GUI) and generates the corresponding design. The GTS PMA/FEC Direct PHY Intel® FPGA IP provides the necessary design files, which must then be processed through the Dynamic Reconfiguration (DR) flow in the Quartus® Prime Pro Edition software.

As part of this flow, a merged DR netlist is created. Additionally, you must integrate this IP with the GTS Dynamic Reconfiguration Controller Intel® FPGA IP that serves as the master controller, enabling the switching between different profiles initially selected in the Reconfigure PHY.

After you select the number of secondary profiles, the corresponding profile tabs are generated in the IP GUI, allowing you to configure various parameters for each one to meet your specific design requirements. These parameters include the PMA data rate, TX and RX datapath options, FEC options, and analog settings. Proper configuration of these settings ensures profile switching, optimized performance and compatibility with the overall design.
Figure 51. Reconfigurable PHY Profile Tabs

Each parameter can be adjusted through the IP GUI to align with the intended use case, allowing flexibility in defining different operational modes. The selected profiles dictate how the multirate IPs dynamically switch between different configurations during operation. It is essential to carefully configure these settings to avoid mismatches or inefficiencies in data transmission.

For a detailed explanation of how to configure each of these parameters, refer to TX Datapath Options, RX Datapath Options, FEC Options, and Analog Parameter Options. These sections provide information on each parameter and their options.