GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs
ID
817660
Date
4/07/2025
Public
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1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP
4. Implementing the GTS System PLL Clocks Intel FPGA IP
5. Implementing the GTS Reset Sequencer Intel FPGA IP
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs
3.1. IP Overview
3.2. Designing with the GTS PMA/FEC Direct PHY Intel FPGA IP
3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP
3.4. Reconfigurable PHY
3.5. Signal and Port Reference
3.6. Bit Mapping for PMA, FEC, and PCS Mode PHY TX and RX Datapath
3.7. Clocking
3.8. Custom Cadence Generation Ports and Logic
3.9. Asserting Reset
3.10. Bonding Implementation
3.11. Configuration Register
3.12. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing
3.13. Configurable Quartus® Prime Software Settings
3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.3.1. Preset IP Parameter Settings
3.3.2. Mode and Common Datapath Options
3.3.3. Reconfigurable PHY Settings
3.3.4. TX Datapath Options
3.3.5. RX Datapath Options
3.3.6. PMA Configuration Rules for Specific Protocol Mode Implementations
3.3.7. FEC Options
3.3.8. PCS Options
3.3.9. Avalon® Memory-Mapped Interface Options
3.3.10. Register Map IP-XACT Support
3.3.11. Analog Parameter Options
3.5.1. TX and RX Parallel and Serial Interface Signals
3.5.2. TX and RX Reference Clock and Clock Output Interface Signals
3.5.3. Reset Signals
3.5.4. FEC Signals
3.5.5. Custom Cadence Control and Status Signals
3.5.6. RX PMA Status Signals
3.5.7. TX and RX PMA and Core Interface FIFO Signals
3.5.8. Avalon Memory-Mapped Interface Signals
3.9.1. Reset Signal Requirements
3.9.2. Power On Reset Requirements
3.9.3. Reset Signals—Block Level
3.9.4. Run-time Reset Sequence—TX
3.9.5. Run-time Reset Sequence—RX
3.9.6. Run-time Reset Sequence—TX + RX
3.9.7. RX Data Loss/CDR Lock Loss (Auto-Recovery)
3.9.8. TX PLL Lock Loss
3.9.9. TX PLL Lock Loss Auto-Recovery (Soft CSR Enabled)
5.1. IP Requirements
5.2. IP Parameters
5.3. IP Port List
5.4. GTS Reset Sequencer Intel FPGA IP General Interface
5.5. GTS Reset Sequencer Intel FPGA IP Design Flow
5.6. GTS Reset Sequencer Intel FPGA IP Use Cases
5.7. Connecting the Reference Clock Buffer Status to the GTS Reset Sequencer Intel® FPGA IP
6.1. Instantiating the GTS PMA/FEC Direct PHY Intel FPGA IP
6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.3. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Functional Description
6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench
6.5. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.6. Hardware Testing the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.7. GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design
6.8. Generating the GTS PMA/FEC Direct PHY Intel® FPGA IP Reconfigurable Example Design
6.9. GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design Functional Description
6.10. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design Testbench
6.11. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design
6.12. Hardware Testing the GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design
4.2. IP Port List
The following table lists the ports for the IP; all ports are 1-bit wide.
Port Name | Direction | Description |
---|---|---|
i_refclk | Input | Reference clock input port. Must be assigned to device reference clock pin. This port can be connected to the local or regional reference clock pins, or the reference clock pins from the HVIO bank, described in System PLL with HVIO Reference Clock . Refer to the device pinout documentation for the available pins. If this port connects to differential pins, you must connect the positive signal of the differential pair to this input port. |
i_refclk_ready | Input | Reference clock ready indicator port. This port is available only when user selects a non- PCIe* mode. Refer to the PCIe* IP user guide for more information about the PCIe* mode. This port indicates when the reference clock becomes available for the first time. |
o_pll_lock | Output | System PLL lock output port. System PLL lock status port which indicates if system PLL is locked to incoming reference clock. |
o_syspll_c0 | Output | System PLL clock output c0 port. This must be connected to system PLL clock input of protocol IP. |