GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs

ID 817660
Date 4/07/2025
Public

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6.7. GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design

The following table lists the Multirate IP (MRIP) example design options available for the GTS PMA/FEC Direct PHY Intel® FPGA IP Reconfigurable PHY.
Table 91.  Example Design Options for the Reconfigurable PHY
Example Design Options Description
MRIP 1 x 10.3125G PMA Direct(P0) to FEC Direct Mode(P1) (System PLL Clocking) Dynamically reconfigure between Profile 0, configured as one NRZ PMA Direct GTS lane, with a throughput of 10.3125 Gbps and Profile 1, configured as one NRZ RS-FEC Direct GTS lane with a throughput of 10.3125 Gbps in System PLL clocking mode.
MRIP 1 x 11.880G (P0) - 1 x 5.940G (P1) - 1 x 2.970G (P2) - 1 x 1.485G (P3) (System PLL Clocking) Dynamically reconfigure between Profile 0, configured as one NRZ PMA Direct GTS lane with a throughput of 11.880 Gbps; Profile 1, configured as one NRZ PMA Direct GTS lane with a throughput of 5.940 Gbps; Profile 2, configured as one NRZ PMA Direct GTS lane with a throughput of 2.970 Gbps; and Profile 3, configured as one NRZ PMA Direct GTS lane with a throughput of 1.485 Gbps, all in System PLL clocking mode.
Note: This example design is currently not supported in hardware in the current Quartus® Prime Pro Edition software release.