GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs
ID
817660
Date
4/07/2025
Public
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1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP
4. Implementing the GTS System PLL Clocks Intel FPGA IP
5. Implementing the GTS Reset Sequencer Intel FPGA IP
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs
3.1. IP Overview
3.2. Designing with the GTS PMA/FEC Direct PHY Intel FPGA IP
3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP
3.4. Reconfigurable PHY
3.5. Signal and Port Reference
3.6. Bit Mapping for PMA, FEC, and PCS Mode PHY TX and RX Datapath
3.7. Clocking
3.8. Custom Cadence Generation Ports and Logic
3.9. Asserting Reset
3.10. Bonding Implementation
3.11. Configuration Register
3.12. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing
3.13. Configurable Quartus® Prime Software Settings
3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.3.1. Preset IP Parameter Settings
3.3.2. Mode and Common Datapath Options
3.3.3. Reconfigurable PHY Settings
3.3.4. TX Datapath Options
3.3.5. RX Datapath Options
3.3.6. PMA Configuration Rules for Specific Protocol Mode Implementations
3.3.7. FEC Options
3.3.8. PCS Options
3.3.9. Avalon® Memory-Mapped Interface Options
3.3.10. Register Map IP-XACT Support
3.3.11. Analog Parameter Options
3.5.1. TX and RX Parallel and Serial Interface Signals
3.5.2. TX and RX Reference Clock and Clock Output Interface Signals
3.5.3. Reset Signals
3.5.4. FEC Signals
3.5.5. Custom Cadence Control and Status Signals
3.5.6. RX PMA Status Signals
3.5.7. TX and RX PMA and Core Interface FIFO Signals
3.5.8. Avalon Memory-Mapped Interface Signals
3.9.1. Reset Signal Requirements
3.9.2. Power On Reset Requirements
3.9.3. Reset Signals—Block Level
3.9.4. Run-time Reset Sequence—TX
3.9.5. Run-time Reset Sequence—RX
3.9.6. Run-time Reset Sequence—TX + RX
3.9.7. RX Data Loss/CDR Lock Loss (Auto-Recovery)
3.9.8. TX PLL Lock Loss
3.9.9. TX PLL Lock Loss Auto-Recovery (Soft CSR Enabled)
5.1. IP Requirements
5.2. IP Parameters
5.3. IP Port List
5.4. GTS Reset Sequencer Intel FPGA IP General Interface
5.5. GTS Reset Sequencer Intel FPGA IP Design Flow
5.6. GTS Reset Sequencer Intel FPGA IP Use Cases
5.7. Connecting the Reference Clock Buffer Status to the GTS Reset Sequencer Intel® FPGA IP
6.1. Instantiating the GTS PMA/FEC Direct PHY Intel FPGA IP
6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.3. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Functional Description
6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench
6.5. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.6. Hardware Testing the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.7. GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design
6.8. Generating the GTS PMA/FEC Direct PHY Intel® FPGA IP Reconfigurable Example Design
6.9. GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design Functional Description
6.10. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design Testbench
6.11. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design
6.12. Hardware Testing the GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design
6.8.2. GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design Directory Structure
The GTS PMA/FEC Direct PHY Intel® FPGA IP Reconfigurable PHY example design contains the following generated files for testbench, simulation, and hardware design testing.
Directory Structure and File Name | Description |
---|---|
Key testbench and simulation files | |
<directphy_example_design>/example_design/rtl/top_tst.sv | Top-level testbench file. The testbench instantiates the top.v Reconfigurable PHY design file. |
<directphy_example_design>/example_design/rtl/testwrap_pma_direct.sv | Test wrapper file that generates and receives the PRBS data stream as well as performs the TX and RX clock output frequency checks. |
Key testbench script files | |
<directphy_example_design>/example_design/testbench/run_vcsmx.sh | The VCS* MX script to run the testbench. |
<directphy_example_design>/example_design/testbench/run_xcelium.sh | The Xcelium* script to run the testbench. |
<directphy_example_design>/example_design/testbench/run_vsim.tcl | The QuestaSim* script to run the testbench. |
<directphy_example_design>/example_design/testbench/run_rivierasim.do | The Riviera-PRO* script to run the testbench. |
Key hardware test design files | |
<design_example_dir>/example_design/ example_design.qpf | Quartus® Prime Pro Edition software project file. |
<design_example_dir>/example_design.qsf | Quartus® Prime Pro Edition software project settings file. |
<design_example_dir>/example_design/rtl/user.sdc | Synopsys* Design Constraints file. You can copy and modify this file for your own Agilex™ 5 device. |
<design_example_dir>/example_design/rtl/top.sv | Top hardware design file. This file instantiates the DUT, JTAG, Avalon® memory-mapped interface, Reset release IP, and the test CSR. |
<design_example_dir>/example_design/hwtest/main_script.tcl | Main script to run hardware test using the system console. |
<design_example_dir>/example_designhwtest/src/parameter.tcl | Stores the configurable variables of the test script. You can modify the JTAG ID and the desired dynamic reconfiguration sequences of the test through the variables in this file. |