GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs

ID 817660
Date 4/07/2025
Public

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6.8.2. GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design Directory Structure

The GTS PMA/FEC Direct PHY Intel® FPGA IP Reconfigurable PHY example design contains the following generated files for testbench, simulation, and hardware design testing.
Table 92.  Example Design Directory Structure and Description
Directory Structure and File Name Description
Key testbench and simulation files
<directphy_example_design>/example_design/rtl/top_tst.sv Top-level testbench file. The testbench instantiates the top.v Reconfigurable PHY design file.
<directphy_example_design>/example_design/rtl/testwrap_pma_direct.sv Test wrapper file that generates and receives the PRBS data stream as well as performs the TX and RX clock output frequency checks.
Key testbench script files
<directphy_example_design>/example_design/testbench/run_vcsmx.sh The VCS* MX script to run the testbench.
<directphy_example_design>/example_design/testbench/run_xcelium.sh The Xcelium* script to run the testbench.
<directphy_example_design>/example_design/testbench/run_vsim.tcl The QuestaSim* script to run the testbench.
<directphy_example_design>/example_design/testbench/run_rivierasim.do The Riviera-PRO* script to run the testbench.
Key hardware test design files
<design_example_dir>/example_design/ example_design.qpf Quartus® Prime Pro Edition software project file.
<design_example_dir>/example_design.qsf Quartus® Prime Pro Edition software project settings file.
<design_example_dir>/example_design/rtl/user.sdc Synopsys* Design Constraints file. You can copy and modify this file for your own Agilex™ 5 device.
<design_example_dir>/example_design/rtl/top.sv Top hardware design file. This file instantiates the DUT, JTAG, Avalon® memory-mapped interface, Reset release IP, and the test CSR.
<design_example_dir>/example_design/hwtest/main_script.tcl Main script to run hardware test using the system console.
<design_example_dir>/example_designhwtest/src/parameter.tcl Stores the configurable variables of the test script. You can modify the JTAG ID and the desired dynamic reconfiguration sequences of the test through the variables in this file.