MIPI D-PHY IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs

ID 817561
Date 6/30/2025
Public
Document Table of Contents

5. Validating the MIPI D-PHY IP

Validate your hardware using the design example generated from the MIPI D-PHY IP. Validating the MIPI DPHY IP design example requires external loopback from the TX link to the RX link.
  1. For external loopback testing with two links on same IO bank, generate one MIPI DPHY IP design example with one TX link and one RX link.
    The design example initiates the data from the traffic generator on the TX link to the traffic checker on the RX link.
  2. Monitor the test conditions for the example design with Signal Tap Logic Analyzer.