MIPI D-PHY IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs

ID 817561
Date 6/30/2025
Public
Document Table of Contents

8.2.1.75. RX__CAL_ALT_W_END_MUX

Offset: 0x65
Default: 0x00
Description: Window end delta from alternate calibration for lane CAL_REG_MUXSEL
Bit Name Access Description
7:0 RX_CAL_ALT_W_END_MUX Read Only Window end delta from alternate calibration for lane CAL_REG_MUXSEL.