MIPI D-PHY IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs

ID 817561
Date 6/30/2025
Public
Document Table of Contents

8.2.1.20. CLK_STATUS

Offset: 0x1D
Default: 0x00
Description:  
Bit Name Access Description
0 CLK_STATUS_INIT_DONE Read Only Clock lane init done.