MIPI D-PHY IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs

ID 817561
Date 6/30/2025
Public
Document Table of Contents

8.2.1.3. D0_CAP

Offset: 0x03
Default: 0x06
Description: Lane 0 Capability
Bit Name Access Description
4:3 D0_CAP_REV_CAP Read Only

Reverse direction ESC mode feature support

00 - None

01 - Events only

11 - All (including LPDT)
2:1 D0_CAP_FWD_ESC_CAP Read Only

Forward direction ESC mode feature support

00 - None

01 - Events only

11 - All (including LPDT)
0 D0_CAP_HS_CAP Read Only

HS capability

0 - Forward only

1 - Forward and reverse (not currently supported)