MIPI D-PHY IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs

ID 817561
Date 6/30/2025
Public
Document Table of Contents

8.2.2.28. TG_PER_SKEW_CAL_LEN

Offset: 0x1D8
Default: 0x04
Description:  
Bit Name Access Description
31:0 TG_PER_SKEW_CAL_LEN Read Write