MIPI D-PHY IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs

ID 817561
Date 6/30/2025
Public
Document Table of Contents

7.2. MIPI D-PHY IP RX

The MIPI D-PHY IP RX architecture includes the following blocks:
  • D-PHY layer. This block handles the external incoming data deserialization with its clocking for both HS and LP modes.
  • Physical coding sub-layer (PCS). Processes the PPI and controls the PHY layer operation including the event between high speed (HS) and low power (LP), D-PHY block initialization and calibration.
  • AXI-Lite. This optional interface controls the protocol timers and registers.
Figure 24. MIPI D-PHY RX Architecture