MIPI D-PHY IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs

ID 817561
Date 6/30/2025
Public
Document Table of Contents

8.2.2.12. LANE_ERROR_SOT_LANES

Offset: 0x189
Default: 0x00
Description: Lane error SOT/SOT SYNC status per lane
Bit Name Access Description
7:0 LANE_ERROR_SOT_LANES Read Only Lane error SOT/SOT SYNC status per lane.