MIPI D-PHY IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs

ID 817561
Date 6/30/2025
Public
Document Table of Contents

8.2.2.10. HS_DONE_LANES

Offset: 0x185
Default: 0x00
Description: HS done per lane (1 bit per lane)
Bit Name Access Description
7:0 HS_DONE_LANES Read Only HS done per lane (1 bit per lane).