Agilex™ 5 FPGAs and SoCs Device Data Sheet

ID 813918
Date 10/13/2025
Public
Document Table of Contents

HPS and SDM I/O Pin Leakage Current

Table 27.  HPS and SDM I/O Pin Leakage Current For specification status, see the Data Sheet Status table
Symbol Description Condition Min Max Unit
II Input pin VI = 0 V to VCCIO_HPS (MAX) VI = 0 V to VCCIO_SDM (MAX) −15 15 µA
Tri-stated I/O pin VO = 0 V to VCCIO_HPS (MAX) VO = 0 V to VCCIO_SDM (MAX) −15 15 µA