1. Agilex™ 5 Embedded Memory Overview
2. Agilex™ 5 Embedded Memory Architecture and Features
3. Agilex™ 5 Embedded Memory Design Considerations
4. Agilex™ 5 Embedded Memory IP References
5. Agilex™ 5 Embedded Memory Debugging
6. Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs Archives
7. Document Revision History for the Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs
2.1. Byte Enable in Agilex™ 5 Embedded Memory Blocks
2.2. Address Hold Support
2.3. Asynchronous Clear and Synchronous Clear
2.4. Memory Blocks Error Correction Code (ECC) Support
2.5. Agilex™ 5 Embedded Memory Clocking Modes
2.6. Agilex™ 5 Embedded Memory Configurations
2.7. Force-to-Zero
2.8. Coherent Read Memory
2.9. Freeze Logic
2.10. True Dual Port Dual Clock Emulator
2.11. Initial Value of Read and Write Address Registers
2.12. Automatic Timing/Power Optimization Feature in M20K Blocks
3.1. Consider the Memory Block Selection
3.2. Consider the Concurrent Write Behavior
3.3. Read-During-Write (RDW)
3.4. Consider Power-Up State and Memory Initialization
3.5. Reduce Power Consumption
3.6. Avoid Providing Non-Deterministic Input
3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously
3.8. Advanced Settings in Quartus® Prime Software for Memory
3.9. Consider the Memory Depth Setting
3.10. Consider Registering the Memory Output
4.1.4.1. RAM: 1-PORT FPGA IP Parameters
4.1.4.2. RAM: 2-PORT FPGA IP Parameters
4.1.4.3. RAM: 4-PORT FPGA IP Parameters
4.1.4.4. ROM: 1-PORT FPGA IP Parameters
4.1.4.5. ROM: 2-PORT FPGA IP Parameters
4.1.4.6. RAM and ROM Parameter Settings
4.1.4.7. Changing Parameter Settings Manually
4.1.4.8. RAM and ROM Interface Signals
4.2.5.1. FIFO Functional Timing Requirements
4.2.5.2. SCFIFO ALMOST_EMPTY Functional Timing
4.2.5.3. FIFO Output Status Flag and Latency
4.2.5.4. FIFO Metastability Protection and Related Options
4.2.5.5. FIFO Synchronous Clear and Asynchronous Clear Effect
4.2.5.6. SCFIFO and DCFIFO Show-Ahead Mode
4.2.5.7. Different Input and Output Width
4.2.5.8. DCFIFO Timing Constraint Setting
4.2.5.9. Gray-Code Counter Transfer at the Clock Domain Crossing
4.2.5.10. Guidelines for Embedded Memory ECC Feature
4.2.5.11. Reset Scheme
4.2.5.8.2.1. SDC Commands
SDC Command | Fitter | Timing Analyzer | Recommended Settings |
---|---|---|---|
set_max_skew 36 | To constraint placement and routing of flops in the multi-bit CDC paths to meet the specified skew requirement among bits. | To analyze whether the specified skew requirement is fully met. Both clock and data paths are taken into consideration. |
Set to less than 1 launch clock. |
set_net_delay | Similar to set_max_skew but without taking clock skews into considerations. To ensure the crossing latency is bounded. |
To analyze whether the specified net delay requirement is fully met. Clock paths are not taken into consideration. |
This is currently set to be less than 1 latch clock. 37 |
set_min_delay/set_max_delay | To relax fitter effort by mimicking the set_false_path command but without overriding other SDCs. 38 |
To relax timing analysis for the setup/hold checks to not fail. 39 |
This is currently set to 100ns/-100ns for max/min. 40 |
36 It can have significant compilation time impact in older Quartus versions without Timing Analyzer 2.
37 For advanced users, you can fine-tune the value based on your design. For instance, if the designs are able to tolerate longer crossing latency (full and empty status can be delayed), this can be relaxed.
38 Without set_false_path (which has the highest precedence and may result in very long insertion delays), Fitter attempts to meet the default setup/hold which is extremely over constraint.
39 Without set_false_path, the CDC paths will be analyzed for default setup/hold, which is extremely over constraint.
40 Expect an approximately 100 ns delay when you observe CDC paths compared to set_false_path.