Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813901
Date 4/15/2025
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 5 Embedded Memory Overview 2. Agilex™ 5 Embedded Memory Architecture and Features 3. Agilex™ 5 Embedded Memory Design Considerations 4. Agilex™ 5 Embedded Memory IP References 5. Agilex™ 5 Embedded Memory Debugging 6. Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs Archives 7. Document Revision History for the Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs
1. Agilex™ 5 Embedded Memory Overview x
1.1. Agilex™ 5 Embedded Memory Features 1.2. Agilex™ 5 Embedded Memory Block Signals
2. Agilex™ 5 Embedded Memory Architecture and Features x
2.1. Byte Enable in Agilex™ 5 Embedded Memory Blocks 2.2. Address Hold Support 2.3. Asynchronous Clear and Synchronous Clear 2.4. Memory Blocks Error Correction Code (ECC) Support 2.5. Agilex™ 5 Embedded Memory Clocking Modes 2.6. Agilex™ 5 Embedded Memory Configurations 2.7. Force-to-Zero 2.8. Coherent Read Memory 2.9. Freeze Logic 2.10. True Dual Port Dual Clock Emulator 2.11. Initial Value of Read and Write Address Registers 2.12. Automatic Timing/Power Optimization Feature in M20K Blocks
2.1. Byte Enable in Agilex™ 5 Embedded Memory Blocks x
2.1.1. Byte Enable Controls 2.1.2. Data Byte Output 2.1.3. Byte Enable Behavior
2.4. Memory Blocks Error Correction Code (ECC) Support x
2.4.1. Error Correction Code Truth Table 2.4.2. Parity Bit 2.4.3. ECC Parity Flip 2.4.4. ECC Read-During-Write Behavior
2.5. Agilex™ 5 Embedded Memory Clocking Modes x
2.5.1. Single Clock Mode 2.5.2. Read/Write Clock Mode 2.5.3. Input/Output Clock Mode 2.5.4. Asynchronous/Synchronous Clears in Clocking Modes 2.5.5. Output Read Data in Simultaneous Read/Write 2.5.6. Independent Clock Enables in Clocking Modes
2.6. Agilex™ 5 Embedded Memory Configurations x
2.6.1. Mixed-Width Port Configurations
2.8. Coherent Read Memory x
2.8.1. Forwarding Logic
2.10. True Dual Port Dual Clock Emulator x
2.10.1. True Dual-Port Mixed Port Read During Write New Data Emulation
3. Agilex™ 5 Embedded Memory Design Considerations x
3.1. Consider the Memory Block Selection 3.2. Consider the Concurrent Write Behavior 3.3. Read-During-Write (RDW) 3.4. Consider Power-Up State and Memory Initialization 3.5. Reduce Power Consumption 3.6. Avoid Providing Non-Deterministic Input 3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously 3.8. Advanced Settings in Quartus® Prime Software for Memory 3.9. Consider the Memory Depth Setting 3.10. Consider Registering the Memory Output
3.3. Read-During-Write (RDW) x
3.3.1. Customize Read-During-Write Behavior
3.3.1. Customize Read-During-Write Behavior x
3.3.1.1. Same-Port Read-During-Write Mode 3.3.1.2. Mixed-Port Read-During-Write Mode 3.3.1.3. Read-During-Write Data Output and Memory Location Behaviors
4. Agilex™ 5 Embedded Memory IP References x
4.1. On-Chip Memory RAM and ROM IPs 4.2. FIFO Intel FPGA IP 4.3. Shift Register (RAM-based) FPGA IP
4.1. On-Chip Memory RAM and ROM IPs x
4.1.1. Release Information for RAM and ROM IPs 4.1.2. Features 4.1.3. Implementation Guide 4.1.4. Parameters and Interface Signals
4.1.2. Features x
4.1.2.1. On-Chip Memory RAM and ROM FPGA IPs
4.1.3. Implementation Guide x
4.1.3.1. Instantiating IP Cores using the Quartus® Prime Parameter Editor
4.1.4. Parameters and Interface Signals x
4.1.4.1. RAM: 1-PORT FPGA IP Parameters 4.1.4.2. RAM: 2-PORT FPGA IP Parameters 4.1.4.3. RAM: 4-PORT FPGA IP Parameters 4.1.4.4. ROM: 1-PORT FPGA IP Parameters 4.1.4.5. ROM: 2-PORT FPGA IP Parameters 4.1.4.6. RAM and ROM Parameter Settings 4.1.4.7. Changing Parameter Settings Manually 4.1.4.8. RAM and ROM Interface Signals
4.2. FIFO Intel FPGA IP x
4.2.1. Release Information for FIFO Intel FPGA IP 4.2.2. Features 4.2.3. Implementation Guide 4.2.4. Parameters and Interface Signals 4.2.5. Design Considerations
4.2.3. Implementation Guide x
4.2.3.1. Instantiating IP Cores using Quartus® Prime Pro Edition Parameter Editor 4.2.3.2. Manual IP Instantiation through HDL
4.2.3.2. Manual IP Instantiation through HDL x
4.2.3.2.1. Verilog HDL Prototype 4.2.3.2.2. VHDL Component Declaration 4.2.3.2.3. VHDL LIBRARY-USE Declaration 4.2.3.2.4. HDL Code from Parameterizable Macros Template 4.2.3.2.5. Coding Example for Manual Instantiation 4.2.3.2.6. Instantiation Template
4.2.4. Parameters and Interface Signals x
4.2.4.1. FIFO Signals 4.2.4.2. FIFO Parameter Settings 4.2.4.3. FIFO Intel FPGA IP Parameters
4.2.5. Design Considerations x
4.2.5.1. FIFO Functional Timing Requirements 4.2.5.2. SCFIFO ALMOST_EMPTY Functional Timing 4.2.5.3. FIFO Output Status Flag and Latency 4.2.5.4. FIFO Metastability Protection and Related Options 4.2.5.5. FIFO Synchronous Clear and Asynchronous Clear Effect 4.2.5.6. SCFIFO and DCFIFO Show-Ahead Mode 4.2.5.7. Different Input and Output Width 4.2.5.8. DCFIFO Timing Constraint Setting 4.2.5.9. Gray-Code Counter Transfer at the Clock Domain Crossing 4.2.5.10. Guidelines for Embedded Memory ECC Feature 4.2.5.11. Reset Scheme
4.2.5.5. FIFO Synchronous Clear and Asynchronous Clear Effect x
4.2.5.5.1. Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO
4.2.5.8. DCFIFO Timing Constraint Setting x
4.2.5.8.1. Embedded Timing Constraint 4.2.5.8.2. User Configurable Timing Constraint
4.2.5.8.2. User Configurable Timing Constraint x
4.2.5.8.2.1. SDC Commands
4.3. Shift Register (RAM-based) FPGA IP x
4.3.1. Release Information for Shift Register (RAM-based) FPGA IP 4.3.2. Features 4.3.3. Implementation Guide 4.3.4. Parameters and Interface Signals
4.3.3. Implementation Guide x
4.3.3.1. Instantiating IP Cores using Quartus® Prime Pro Edition Parameter Editor
4.3.4. Parameters and Interface Signals x
4.3.4.1. Shift Register (RAM-based) FPGA IP Parameter Settings 4.3.4.2. Shift Register Ports and Parameters Setting
1. Agilex™ 5 Embedded Memory Overview
2. Agilex™ 5 Embedded Memory Architecture and Features
3. Agilex™ 5 Embedded Memory Design Considerations
4. Agilex™ 5 Embedded Memory IP References
5. Agilex™ 5 Embedded Memory Debugging
6. Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs Archives
7. Document Revision History for the Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs

7. Document Revision History for the Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs

Document Version Quartus® Prime Version Changes
2025.04.15 25.1
  • Removed the High Speed (HS) mode or Low Power (LP) mode of the timing/power optimization feature:
    • Updated topic title Timing/Power Optimization Feature in M20K Blocks to Automatic Timing/Power Optimization Feature in M20K Blocks.
    • Updated the description in the Automatic Timing/Power Optimization Feature in M20K Blocks topic.
    • Removed a bullet point about the low-power mode in the Reduce Power Consumption topic.
    • Removed Which timing/power optimization option do you want to use? parameter in the RAM: 1-PORT FPGA IP Parameter Settings table.
    • Removed Which timing/power optimization option do you want to use? parameter in the RAM: 2-PORT FPGA IP Parameter Settings table.
    • Removed Which timing/power optimization option do you want to use? parameter in the RAM: 4-PORT FPGA IP Parameter Settings table.
    • Removed Which timing/power optimization option do you want to use? parameter in the ROM: 1-PORT Parameters— Performance Optimization table.
    • Removed Which timing/power optimization option do you want to use in the ROM: 2-PORT FPGA IP Parameter Settings.
    • Removed optimization_option in the Parameters for altera_syncram table.
  • Added a step to insert sync_fifo and async_fifo in the HDL Code from Parameterizable Macros Template topic.
  • Added FIFO Parameters (SCFIFO and DCFIFO) table.
2025.02.21 24.3
  • Added a Features topic for FIFO FPGA IP .
  • Added eccstatus signal in the Input and Output Ports Description table in the FIFO Signals topic.
  • Added a footnote for byteena signal in the Input and Output Ports Description table in the FIFO Signals topic.
  • Removed the Design Example topic in the Design Considerations topic for FIFO FPGA IP.
2025.01.23 24.3
  • Updated the structure of the Agilex™ 5 Embedded Memory IP References topic to reorganize the subtopics of each IP into the following:
    • Release Information
    • Features
    • Implementation
    • Parameter and Interface Signals
  • Updated Asynchronous Clear and Synchronous Clear topic to update the bullet point about the description of the synchronous clear (sclr).
  • Updated Shift Register (RAM-based) FPGA IP Parameter Settings table to add the range of valid input values for How wide should the "shiftin" input and the "shiftout" output buses be? parameter.
2024.12.17 24.3 Removed rdaddress port from SCLR options in the RAM: 2-PORT FPGA IP Parameter Settings table.
2024.11.04 24.3
  • Added clarification on existing topics:
    • Updated description in the Coherent Read Memory topic.
    • Updated Simplified Block Diagram of Coherent Read Memory Circuitry figure.
    • Updated Address Hold During Read Cycle and Address Hold During Write Cycle figures.
    • Updated Pipelining Waveform When Output of M20K Blocks is Unregistered figure.
    • Updated Pipelining Waveform When Output of M20K Blocks is Registered figure.
    • Added Same-Port Read-During-Write: Old Data Mode figure.
    • Changed clk_a&b signal name to clk in the following diagrams:
      • Mixed-Port Read-During-Write: New Data Mode
      • Mixed-Port Read-During-Write: Old Data Mode
      • Mixed-Port Read-During-Write: Don't Care Mode
  • Updated the following in the RAM: 2-PORT Intel FPGA IP Parameter Settings table:
    • Updated the Description column for the Which clocking method do you want to use? parameter for Parameter Settings: Clks/Rd, Byte En.
    • Updated the Legal Values column for What is the width of a byte for byte enables? parameter for Parameter Settings: Clks/Rd, Byte En.
2024.09.30 24.2
  • Updated the description in the Coherent Read Memory topic.
  • Updated Coherent Read Memory Behavior for Agilex™ 5 Blocks figure.
  • Updated description in the True Dual-Port Mixed Port Read During Write New Data Emulation topic.
  • Updated the following figures:
    • Pipelining Waveform When Output of M20K Blocks is Unregistered
    • Pipelining Waveform When Output of M20K Blocks is Registered
2024.09.03 24.2 Added a new topic: Read During Write Data Output and Memory Location Behaviors.
2024.08.02 24.2
  • Updated the description in the Agilex™ 5 Embedded Memory Features topic.
  • Updated Agilex 5 Embedded Memory Features table.
  • Added Agilex 5 Embedded Memory Block Signals topic.
  • Updated the description Agilex™ 5 Embedded Memory Architecture and Features topic.
  • Updated the description in the Byte Enable in Agilex™ 5 Embedded Memory Blocks topic.
  • Updated description in the Data Byte Output topic.
  • Updated signal name inclock to clk for Byte Enable Functional Waveform diagram.
  • Changed Address Clock Enable Support topic title to Address Hold Support and updated its description..
  • Updated the description in the Asynchronous Clear and Synchronous Clear.
  • Updated Behavior of Asynchronous Clear and Synchronous Clear in Registered Mode diagram.
  • Updated Behavior When Asynchronous Clear is Used on Read Address Register in Registered and Unregistered Modes diagram.
  • Updated the description in the Memory Blocks Error Correction Code (ECC) Support topic.
  • Updated the description for the ECC Read-During-Write Behavior topic.
  • Removed ECC Block Diagram for M20K Memory and updated ECC Status Flags Truth Table for M20K table in the Error Correction Code Truth Table topic.
  • Updated Read/Write Clock Mode topic.
  • Updated Input/Output Clock Mode topic.
  • Updated Mixed-Width Port Configurations topic.
  • Updated True Dual Port Dual Clock Emulator topic.
  • Added True Dual-Port Mixed Port Read During Write New Data Emulation topic.
  • Updated Simple Dual-Port RAM with Registered Output Timing Diagram.
  • Updated Consider the Concurrent Write Behavior topic.
  • Added Read-During-Write (RDW) topic.
  • Updated Same-Port Read-During-Write Mode topic.
  • Updated Output Modes for Embedded Memory Blocks in Same-Port Read-During-Write Mode to add a note for the Don't Care output mode.
  • Updated Mixed-Port Read-During-Write Mode topic.
  • Updated Consider Power-Up State and Memory Initialization topic.
  • Added M20K memory type for New Data output mode in the Output Modes for RAM in Mixed-Port Read-During-Write Mode table.
  • Updated the header description for Parameter Settings: Mixed Port Read-During-Write in the RAM: 2-PORT Intel® FPGA IP Parameters table.
  • Updated description for read_during_write_mode_mixed_ports in the Parameters for altera_syncram table.
  • Updated description for addresstall_a, wraddresstall, and rdaddresstall in the Interface Signals of the Agilex 5 RAM and ROM IPs table.
  • Updated the description for sclr and aclr ports in the Input and Output Ports Description table.
  • Removed mentions of Agilex 5 in the following (editorial edits to the text only; no change in the technical information):
    • The description for wrreq port in the Input and Output Ports Description table.
    • The note in the FIFO Synchronous Clear and Asynchronous Clear Effect topic.
    • The footnote for Effects on the q output for normal output modes mode in the Asynchronous Clear in DCFIFO table.
    • The Guidelines for Embedded Memory ECC Feature topic.
    • The Reset Scheme topic.
2024.04.01 24.1 Initial release.
Level Two Title