Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813901
Date 4/15/2025
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 5 Embedded Memory Overview 2. Agilex™ 5 Embedded Memory Architecture and Features 3. Agilex™ 5 Embedded Memory Design Considerations 4. Agilex™ 5 Embedded Memory IP References 5. Agilex™ 5 Embedded Memory Debugging 6. Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs Archives 7. Document Revision History for the Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs
1. Agilex™ 5 Embedded Memory Overview x
1.1. Agilex™ 5 Embedded Memory Features 1.2. Agilex™ 5 Embedded Memory Block Signals
2. Agilex™ 5 Embedded Memory Architecture and Features x
2.1. Byte Enable in Agilex™ 5 Embedded Memory Blocks 2.2. Address Hold Support 2.3. Asynchronous Clear and Synchronous Clear 2.4. Memory Blocks Error Correction Code (ECC) Support 2.5. Agilex™ 5 Embedded Memory Clocking Modes 2.6. Agilex™ 5 Embedded Memory Configurations 2.7. Force-to-Zero 2.8. Coherent Read Memory 2.9. Freeze Logic 2.10. True Dual Port Dual Clock Emulator 2.11. Initial Value of Read and Write Address Registers 2.12. Automatic Timing/Power Optimization Feature in M20K Blocks
2.1. Byte Enable in Agilex™ 5 Embedded Memory Blocks x
2.1.1. Byte Enable Controls 2.1.2. Data Byte Output 2.1.3. Byte Enable Behavior
2.4. Memory Blocks Error Correction Code (ECC) Support x
2.4.1. Error Correction Code Truth Table 2.4.2. Parity Bit 2.4.3. ECC Parity Flip 2.4.4. ECC Read-During-Write Behavior
2.5. Agilex™ 5 Embedded Memory Clocking Modes x
2.5.1. Single Clock Mode 2.5.2. Read/Write Clock Mode 2.5.3. Input/Output Clock Mode 2.5.4. Asynchronous/Synchronous Clears in Clocking Modes 2.5.5. Output Read Data in Simultaneous Read/Write 2.5.6. Independent Clock Enables in Clocking Modes
2.6. Agilex™ 5 Embedded Memory Configurations x
2.6.1. Mixed-Width Port Configurations
2.8. Coherent Read Memory x
2.8.1. Forwarding Logic
2.10. True Dual Port Dual Clock Emulator x
2.10.1. True Dual-Port Mixed Port Read During Write New Data Emulation
3. Agilex™ 5 Embedded Memory Design Considerations x
3.1. Consider the Memory Block Selection 3.2. Consider the Concurrent Write Behavior 3.3. Read-During-Write (RDW) 3.4. Consider Power-Up State and Memory Initialization 3.5. Reduce Power Consumption 3.6. Avoid Providing Non-Deterministic Input 3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously 3.8. Advanced Settings in Quartus® Prime Software for Memory 3.9. Consider the Memory Depth Setting 3.10. Consider Registering the Memory Output
3.3. Read-During-Write (RDW) x
3.3.1. Customize Read-During-Write Behavior
3.3.1. Customize Read-During-Write Behavior x
3.3.1.1. Same-Port Read-During-Write Mode 3.3.1.2. Mixed-Port Read-During-Write Mode 3.3.1.3. Read-During-Write Data Output and Memory Location Behaviors
4. Agilex™ 5 Embedded Memory IP References x
4.1. On-Chip Memory RAM and ROM IPs 4.2. FIFO Intel FPGA IP 4.3. Shift Register (RAM-based) FPGA IP
4.1. On-Chip Memory RAM and ROM IPs x
4.1.1. Release Information for RAM and ROM IPs 4.1.2. Features 4.1.3. Implementation Guide 4.1.4. Parameters and Interface Signals
4.1.2. Features x
4.1.2.1. On-Chip Memory RAM and ROM FPGA IPs
4.1.3. Implementation Guide x
4.1.3.1. Instantiating IP Cores using the Quartus® Prime Parameter Editor
4.1.4. Parameters and Interface Signals x
4.1.4.1. RAM: 1-PORT FPGA IP Parameters 4.1.4.2. RAM: 2-PORT FPGA IP Parameters 4.1.4.3. RAM: 4-PORT FPGA IP Parameters 4.1.4.4. ROM: 1-PORT FPGA IP Parameters 4.1.4.5. ROM: 2-PORT FPGA IP Parameters 4.1.4.6. RAM and ROM Parameter Settings 4.1.4.7. Changing Parameter Settings Manually 4.1.4.8. RAM and ROM Interface Signals
4.2. FIFO Intel FPGA IP x
4.2.1. Release Information for FIFO Intel FPGA IP 4.2.2. Features 4.2.3. Implementation Guide 4.2.4. Parameters and Interface Signals 4.2.5. Design Considerations
4.2.3. Implementation Guide x
4.2.3.1. Instantiating IP Cores using Quartus® Prime Pro Edition Parameter Editor 4.2.3.2. Manual IP Instantiation through HDL
4.2.3.2. Manual IP Instantiation through HDL x
4.2.3.2.1. Verilog HDL Prototype 4.2.3.2.2. VHDL Component Declaration 4.2.3.2.3. VHDL LIBRARY-USE Declaration 4.2.3.2.4. HDL Code from Parameterizable Macros Template 4.2.3.2.5. Coding Example for Manual Instantiation 4.2.3.2.6. Instantiation Template
4.2.4. Parameters and Interface Signals x
4.2.4.1. FIFO Signals 4.2.4.2. FIFO Parameter Settings 4.2.4.3. FIFO Intel FPGA IP Parameters
4.2.5. Design Considerations x
4.2.5.1. FIFO Functional Timing Requirements 4.2.5.2. SCFIFO ALMOST_EMPTY Functional Timing 4.2.5.3. FIFO Output Status Flag and Latency 4.2.5.4. FIFO Metastability Protection and Related Options 4.2.5.5. FIFO Synchronous Clear and Asynchronous Clear Effect 4.2.5.6. SCFIFO and DCFIFO Show-Ahead Mode 4.2.5.7. Different Input and Output Width 4.2.5.8. DCFIFO Timing Constraint Setting 4.2.5.9. Gray-Code Counter Transfer at the Clock Domain Crossing 4.2.5.10. Guidelines for Embedded Memory ECC Feature 4.2.5.11. Reset Scheme
4.2.5.5. FIFO Synchronous Clear and Asynchronous Clear Effect x
4.2.5.5.1. Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO
4.2.5.8. DCFIFO Timing Constraint Setting x
4.2.5.8.1. Embedded Timing Constraint 4.2.5.8.2. User Configurable Timing Constraint
4.2.5.8.2. User Configurable Timing Constraint x
4.2.5.8.2.1. SDC Commands
4.3. Shift Register (RAM-based) FPGA IP x
4.3.1. Release Information for Shift Register (RAM-based) FPGA IP 4.3.2. Features 4.3.3. Implementation Guide 4.3.4. Parameters and Interface Signals
4.3.3. Implementation Guide x
4.3.3.1. Instantiating IP Cores using Quartus® Prime Pro Edition Parameter Editor
4.3.4. Parameters and Interface Signals x
4.3.4.1. Shift Register (RAM-based) FPGA IP Parameter Settings 4.3.4.2. Shift Register Ports and Parameters Setting
1. Agilex™ 5 Embedded Memory Overview
2. Agilex™ 5 Embedded Memory Architecture and Features
3. Agilex™ 5 Embedded Memory Design Considerations
4. Agilex™ 5 Embedded Memory IP References
5. Agilex™ 5 Embedded Memory Debugging
6. Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs Archives
7. Document Revision History for the Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs

3.3.1.1. Same-Port Read-During-Write Mode

Same-port read-during-write mode refers to a memory access scenario where a single port of a memory device performs both a read and a write operation to the same memory address simultaneously.

The same-port read-during-write mode applies to a single-port RAM, simple quad-port RAM, or the same port of a true dual-port RAM.

Table 12.  Output Modes for Embedded Memory Blocks in Same-Port Read-During-Write ModeThis table lists the available output modes if you select the embedded memory blocks in the same-port read-during-write mode.
Output Mode Memory Type Description Supported Operation Mode
New Data M20K The new data is available on the rising edge of the same clock cycle on which the new data is written.
  • True Dual-port RAM
Old Data M20K The RAM output reflects the old data at that address before the write operation proceeds.
  • Single-port RAM
Don't Care
Note: This output mode is applicable in simulation only.
M20K, MLAB The RAM produces Don't Care values for a read-during-write operation.
  • Quad-port RAM (for M20K only)
  • Single-port RAM
Figure 23. Same-Port Read-During-Write: New Data ModeThis figure shows sample functional waveforms of same-port read-during-write behavior in the New Data mode.


Figure 24. Same-Port Read-During-Write: Old Data Mode
Figure 25. Same-Port Read-During-Write: Don't Care ModeThis figure shows sample functional waveforms of same-port read-during-write behavior in the Don't Care mode.
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