1. Agilex™ 5 Embedded Memory Overview
2. Agilex™ 5 Embedded Memory Architecture and Features
3. Agilex™ 5 Embedded Memory Design Considerations
4. Agilex™ 5 Embedded Memory IP References
5. Agilex™ 5 Embedded Memory Debugging
6. Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs Archives
7. Document Revision History for the Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs
2.1. Byte Enable in Agilex™ 5 Embedded Memory Blocks
2.2. Address Hold Support
2.3. Asynchronous Clear and Synchronous Clear
2.4. Memory Blocks Error Correction Code (ECC) Support
2.5. Agilex™ 5 Embedded Memory Clocking Modes
2.6. Agilex™ 5 Embedded Memory Configurations
2.7. Force-to-Zero
2.8. Coherent Read Memory
2.9. Freeze Logic
2.10. True Dual Port Dual Clock Emulator
2.11. Initial Value of Read and Write Address Registers
2.12. Automatic Timing/Power Optimization Feature in M20K Blocks
3.1. Consider the Memory Block Selection
3.2. Consider the Concurrent Write Behavior
3.3. Read-During-Write (RDW)
3.4. Consider Power-Up State and Memory Initialization
3.5. Reduce Power Consumption
3.6. Avoid Providing Non-Deterministic Input
3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously
3.8. Advanced Settings in Quartus® Prime Software for Memory
3.9. Consider the Memory Depth Setting
3.10. Consider Registering the Memory Output
4.1.4.1. RAM: 1-PORT FPGA IP Parameters
4.1.4.2. RAM: 2-PORT FPGA IP Parameters
4.1.4.3. RAM: 4-PORT FPGA IP Parameters
4.1.4.4. ROM: 1-PORT FPGA IP Parameters
4.1.4.5. ROM: 2-PORT FPGA IP Parameters
4.1.4.6. RAM and ROM Parameter Settings
4.1.4.7. Changing Parameter Settings Manually
4.1.4.8. RAM and ROM Interface Signals
4.2.5.1. FIFO Functional Timing Requirements
4.2.5.2. SCFIFO ALMOST_EMPTY Functional Timing
4.2.5.3. FIFO Output Status Flag and Latency
4.2.5.4. FIFO Metastability Protection and Related Options
4.2.5.5. FIFO Synchronous Clear and Asynchronous Clear Effect
4.2.5.6. SCFIFO and DCFIFO Show-Ahead Mode
4.2.5.7. Different Input and Output Width
4.2.5.8. DCFIFO Timing Constraint Setting
4.2.5.9. Gray-Code Counter Transfer at the Clock Domain Crossing
4.2.5.10. Guidelines for Embedded Memory ECC Feature
4.2.5.11. Reset Scheme
4.1.3.1. Instantiating IP Cores using the Quartus® Prime Parameter Editor
Quickly configure the on-chip memory RAM and ROM FPGA IP cores in the Quartus® Prime parameter editor. Double-click any component in the IP Catalog to launch the parameter editor. The parameter editor allows you to define a custom variation of the embedded memory IP core. The parameter editor generates the IP variation synthesis and optional simulation files, and adds the .ip file representing the variation to your project automatically.
Follow these steps to locate, instantiate, and customize an embedded memory IP core in the parameter editor:
- Create or open a Quartus® Prime project (.qpf) to contain the instantiated IP variation.
- In Tools > IP Catalog, double-click the name of the IP core to customize. To locate a specific component, type some or all of the component's name in the IP Catalog search box.
Figure 30. On-Chip Memory IP Cores in IP Catalog
The New IP Variant window appears. - Specify a top-level name for your custom IP variation and click OK.
Do not include spaces in IP variation names or paths.The parameter editor appears. The parameter editor saves the IP variation settings in a file named <your_ip> .ip.
- Set the parameter values in the parameter editor and view the block diagram for the component.
Note: Refer to your IP core user guide for information about specific IP core parameters.
- Optionally, select preset parameter values if provided for your IP core. Presets specify initial parameter values for specific applications.
- Specify parameters defining the IP core functionality, port configurations, and device-specific features.
- Specify options for processing the IP core files in other EDA tools.
The System Messages tab at displays any errors in the IP parameters. - Click Generate HDL. The Generation window appears.
- Specify the output file generation options, and then click Generate. The synthesis and simulation files generate according to your specifications.
- To generate a simulation testbench, click Generate > Generate Testbench System. Specify testbench generation options, and then click Generate.
- To generate an HDL instantiation template that you can copy and paste into your text editor, click Generate > Show Instantiation Template.
- Click Finish. Click Yes if prompted to add files representing the IP variation to your project.
- After generating and instantiating your IP variation, make appropriate pin assignments to connect ports.
Note: Some IPs generate different HDL implementations according to the IP parameters. The underlying RTL of these IPs contains a unique hash code that prevents module name collisions between different variations of an IP. This unique code remains consistent, given the same IP settings and software version during IP generation. The unique code can change if you edit the IP's parameters or upgrade the IP version. To avoid dependency on these unique codes in your simulation environment, refer to the Generating a Combined Simulator Setup Script section of the Introduction to FPGA IP Cores.
Related Information