Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs

ID 813901
Date 4/15/2025
Public
Document Table of Contents

2.12. Automatic Timing/Power Optimization Feature in M20K Blocks

In Agilex™ 5 devices, Quartus® Prime Pro Edition automatically optimizes the timing and power characteristics of M20K blocks based on your design requirements. The software dynamically determines whether to prioritize performance or power savings. This ensures optimal efficiency without user intervention.

Note: The timing/power optimization feature is automatically applied when using the M20K memory type in the Agilex™ 5 devices. No additional configuration is required in the parameter editors of RAM/ROM IP cores.