1. Agilex™ 5 Embedded Memory Overview
2. Agilex™ 5 Embedded Memory Architecture and Features
3. Agilex™ 5 Embedded Memory Design Considerations
4. Agilex™ 5 Embedded Memory IP References
5. Agilex™ 5 Embedded Memory Debugging
6. Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs Archives
7. Document Revision History for the Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs
2.1. Byte Enable in Agilex™ 5 Embedded Memory Blocks
2.2. Address Hold Support
2.3. Asynchronous Clear and Synchronous Clear
2.4. Memory Blocks Error Correction Code (ECC) Support
2.5. Agilex™ 5 Embedded Memory Clocking Modes
2.6. Agilex™ 5 Embedded Memory Configurations
2.7. Force-to-Zero
2.8. Coherent Read Memory
2.9. Freeze Logic
2.10. True Dual Port Dual Clock Emulator
2.11. Initial Value of Read and Write Address Registers
2.12. Automatic Timing/Power Optimization Feature in M20K Blocks
3.1. Consider the Memory Block Selection
3.2. Consider the Concurrent Write Behavior
3.3. Read-During-Write (RDW)
3.4. Consider Power-Up State and Memory Initialization
3.5. Reduce Power Consumption
3.6. Avoid Providing Non-Deterministic Input
3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously
3.8. Advanced Settings in Quartus® Prime Software for Memory
3.9. Consider the Memory Depth Setting
3.10. Consider Registering the Memory Output
4.1.4.1. RAM: 1-PORT FPGA IP Parameters
4.1.4.2. RAM: 2-PORT FPGA IP Parameters
4.1.4.3. RAM: 4-PORT FPGA IP Parameters
4.1.4.4. ROM: 1-PORT FPGA IP Parameters
4.1.4.5. ROM: 2-PORT FPGA IP Parameters
4.1.4.6. RAM and ROM Parameter Settings
4.1.4.7. Changing Parameter Settings Manually
4.1.4.8. RAM and ROM Interface Signals
4.2.5.1. FIFO Functional Timing Requirements
4.2.5.2. SCFIFO ALMOST_EMPTY Functional Timing
4.2.5.3. FIFO Output Status Flag and Latency
4.2.5.4. FIFO Metastability Protection and Related Options
4.2.5.5. FIFO Synchronous Clear and Asynchronous Clear Effect
4.2.5.6. SCFIFO and DCFIFO Show-Ahead Mode
4.2.5.7. Different Input and Output Width
4.2.5.8. DCFIFO Timing Constraint Setting
4.2.5.9. Gray-Code Counter Transfer at the Clock Domain Crossing
4.2.5.10. Guidelines for Embedded Memory ECC Feature
4.2.5.11. Reset Scheme
3.9. Consider the Memory Depth Setting
Use an even number to specify the memory depth or words. If you specify an odd number, the Quartus® Prime software increases the number by one during RTL generation to make it an even number.
For example, if you input "255" for the memory depth, Quartus® Prime software generates an RTL with memory depth of 256.
If you specify an odd-sized memory depth in a .mif or .hex, the Quartus® Prime software issues this warning during compilation:
Critical Warning (127005): Memory depth (256) in the design file differs from memory depth (255) in the Memory Initialization File <hex file> – setting the initial value for remaining addresses to 0.