1. Agilex™ 5 Embedded Memory Overview
2. Agilex™ 5 Embedded Memory Architecture and Features
3. Agilex™ 5 Embedded Memory Design Considerations
4. Agilex™ 5 Embedded Memory IP References
5. Agilex™ 5 Embedded Memory Debugging
6. Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs Archives
7. Document Revision History for the Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs
2.1. Byte Enable in Agilex™ 5 Embedded Memory Blocks
2.2. Address Hold Support
2.3. Asynchronous Clear and Synchronous Clear
2.4. Memory Blocks Error Correction Code (ECC) Support
2.5. Agilex™ 5 Embedded Memory Clocking Modes
2.6. Agilex™ 5 Embedded Memory Configurations
2.7. Force-to-Zero
2.8. Coherent Read Memory
2.9. Freeze Logic
2.10. True Dual Port Dual Clock Emulator
2.11. Initial Value of Read and Write Address Registers
2.12. Automatic Timing/Power Optimization Feature in M20K Blocks
3.1. Consider the Memory Block Selection
3.2. Consider the Concurrent Write Behavior
3.3. Read-During-Write (RDW)
3.4. Consider Power-Up State and Memory Initialization
3.5. Reduce Power Consumption
3.6. Avoid Providing Non-Deterministic Input
3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously
3.8. Advanced Settings in Quartus® Prime Software for Memory
3.9. Consider the Memory Depth Setting
3.10. Consider Registering the Memory Output
4.1.4.1. RAM: 1-PORT FPGA IP Parameters
4.1.4.2. RAM: 2-PORT FPGA IP Parameters
4.1.4.3. RAM: 4-PORT FPGA IP Parameters
4.1.4.4. ROM: 1-PORT FPGA IP Parameters
4.1.4.5. ROM: 2-PORT FPGA IP Parameters
4.1.4.6. RAM and ROM Parameter Settings
4.1.4.7. Changing Parameter Settings Manually
4.1.4.8. RAM and ROM Interface Signals
4.2.5.1. FIFO Functional Timing Requirements
4.2.5.2. SCFIFO ALMOST_EMPTY Functional Timing
4.2.5.3. FIFO Output Status Flag and Latency
4.2.5.4. FIFO Metastability Protection and Related Options
4.2.5.5. FIFO Synchronous Clear and Asynchronous Clear Effect
4.2.5.6. SCFIFO and DCFIFO Show-Ahead Mode
4.2.5.7. Different Input and Output Width
4.2.5.8. DCFIFO Timing Constraint Setting
4.2.5.9. Gray-Code Counter Transfer at the Clock Domain Crossing
4.2.5.10. Guidelines for Embedded Memory ECC Feature
4.2.5.11. Reset Scheme
4.2.5.3. FIFO Output Status Flag and Latency
The main concern in most FIFO design is the output latency of the read and write status signals.
Output Mode | Optimization Option 22 | Output Latency (in number of clock cycles) |
---|---|---|
Normal 23 | Speed | wrreq / rdreq to full: 1 |
wrreq to empty: 2 | ||
rdreq to empty: 1 | ||
wrreq / rdreq to usedw[]: 1 | ||
rdreq to q[]: 1 | ||
Area | wrreq / rdreq to full: 1 | |
wrreq / rdreq to empty : 1 | ||
wrreq / rdreq to usedw[] : 1 | ||
rdreq to q[]: 1 | ||
Show-ahead 23 | Speed | wrreq / rdreq to full: 1 |
wrreq to empty: 3 | ||
rdreq to empty: 1 | ||
wrreq / rdreq to usedw[]: 1 | ||
wrreq to q[]: 3 | ||
rdreq to q[]: 1 | ||
Area | wrreq / rdreq to full: 1 | |
wrreq to empty: 2 | ||
rdreq to empty: 1 | ||
wrreq / rdreq to usedw[]: 1 | ||
wrreq to q[]: 2 | ||
rdreq to q[]: 1 |
Output Mode | Optimization Option 24 | Output Latency (in number of clock cycles) |
---|---|---|
Normal 25 | Speed | wrreq / rdreq to full: 1 |
wrreq to empty: 1 | ||
rdreq to empty: 1 | ||
wrreq / rdreq to usedw[]: 1 | ||
rdreq to q[]: 1 | ||
Area | wrreq / rdreq to full: 1 | |
wrreq / rdreq to empty : 1 | ||
wrreq / rdreq to usedw[] : 1 | ||
rdreq to q[]: 1 | ||
Show-ahead 25 | Speed | wrreq / rdreq to full: 1 |
wrreq to empty: 1 | ||
rdreq to empty: 1 | ||
wrreq / rdreq to usedw[]: 1 | ||
wrreq to q[]: 1 | ||
rdreq to q[]: 1 | ||
Area | wrreq / rdreq to full: 1 | |
wrreq to empty: 1 | ||
rdreq to empty: 1 | ||
wrreq / rdreq to usedw[]: 1 | ||
wrreq to q[]: 1 | ||
rdreq to q[]: 1 |
Output Latency (in number of clock cycles) |
---|
wrreq to wrfull: 1 wrclk |
wrreq to rdfull: 2 wrclk cycles + following n rdclk 26 |
wrreq to wrempty: 1 wrclk |
wrreq to rdempty: 2 wrclk 27 + following n rdclk 27 |
wrreq to wrusedw[]: 2 wrclk |
wrreq to rdusedw[]: 2 wrclk + following n + 1 rdclk 27 |
wrreq to q[]: 1 wrclk + following 1 rdclk 27 |
rdreq to rdempty: 1 rdclk |
rdreq to wrempty: 1 rdclk + following n wrclk 27 |
rdreq to rfull: 1 rdclk |
rdreq to wrfull: 1 rdclk + following n wrclk 27 |
rdreq to rdusedw[]: 2 rdclk |
rdreq to wrusedw[]: 1 rdclk + following n + 1 wrclk 27 |
rdreq to q[]: 1 rdclk |
22 Speed optimization is equivalent to setting the ADD_RAM_OUTPUT_REGISTER parameter to ON. Setting the parameter to OFF is equivalent to area optimization.
23 Normal output mode is equivalent to setting the LPM_SHOWAHEAD parameter to OFF. For Show-ahead mode, the parameter is set to ON.
24 Speed optimization is equivalent to setting the ADD_RAM_OUTPUT_REGISTER parameter to ON. Setting the parameter to OFF is equivalent to area optimization.
25 Normal output mode is equivalent to setting the LPM_SHOWAHEAD parameter to OFF. For Show-ahead mode, the parameter is set to ON.
26 The number of n cycles for rdclk and wrclk is equivalent to the number of synchronization stages and are related to the WRSYNC_DELAYPIPE and RDSYNC_DELAYPIPE parameters. For more information about how the actual synchronization stage (n) is related to the parameters set for different target device, refer to FIFO Metastability Protection and Related Options .
27 This is applied only to Show-ahead output modes. Show-ahead output mode is equivalent to setting the LPM_SHOWAHEAD parameter to ON.