Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs

ID 813901
Date 4/15/2025
Public
Document Table of Contents

3.2. Consider the Concurrent Write Behavior

By default, concurrent writes can corrupt the memory content, leading to unpredictable data. The Agilex™ 5 embedded memory blocks offer predictable write behavior even when two write operations target the same memory location at the same time (concurrent writes).

Enabling Non-Corruptible Writes (Simulation)

To ensure data integrity during concurrent writes, activate the "ENA_NON_CORRUPT=1" option within your simulator setup script. This option enables a prioritized write mechanism.

Prioritized Writes with Time-Division Multiplexing (Hardware)

In actual hardware, Time-Division Multiplexing (TDM) guarantees a specific write order to ensure data from Port A prevails in case of contention:

  1. First, write the value from Port B.
  2. Next, write the value from Port A.