Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813901
Date 4/15/2025
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 5 Embedded Memory Overview 2. Agilex™ 5 Embedded Memory Architecture and Features 3. Agilex™ 5 Embedded Memory Design Considerations 4. Agilex™ 5 Embedded Memory IP References 5. Agilex™ 5 Embedded Memory Debugging 6. Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs Archives 7. Document Revision History for the Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs
1. Agilex™ 5 Embedded Memory Overview x
1.1. Agilex™ 5 Embedded Memory Features 1.2. Agilex™ 5 Embedded Memory Block Signals
2. Agilex™ 5 Embedded Memory Architecture and Features x
2.1. Byte Enable in Agilex™ 5 Embedded Memory Blocks 2.2. Address Hold Support 2.3. Asynchronous Clear and Synchronous Clear 2.4. Memory Blocks Error Correction Code (ECC) Support 2.5. Agilex™ 5 Embedded Memory Clocking Modes 2.6. Agilex™ 5 Embedded Memory Configurations 2.7. Force-to-Zero 2.8. Coherent Read Memory 2.9. Freeze Logic 2.10. True Dual Port Dual Clock Emulator 2.11. Initial Value of Read and Write Address Registers 2.12. Automatic Timing/Power Optimization Feature in M20K Blocks
2.1. Byte Enable in Agilex™ 5 Embedded Memory Blocks x
2.1.1. Byte Enable Controls 2.1.2. Data Byte Output 2.1.3. Byte Enable Behavior
2.4. Memory Blocks Error Correction Code (ECC) Support x
2.4.1. Error Correction Code Truth Table 2.4.2. Parity Bit 2.4.3. ECC Parity Flip 2.4.4. ECC Read-During-Write Behavior
2.5. Agilex™ 5 Embedded Memory Clocking Modes x
2.5.1. Single Clock Mode 2.5.2. Read/Write Clock Mode 2.5.3. Input/Output Clock Mode 2.5.4. Asynchronous/Synchronous Clears in Clocking Modes 2.5.5. Output Read Data in Simultaneous Read/Write 2.5.6. Independent Clock Enables in Clocking Modes
2.6. Agilex™ 5 Embedded Memory Configurations x
2.6.1. Mixed-Width Port Configurations
2.8. Coherent Read Memory x
2.8.1. Forwarding Logic
2.10. True Dual Port Dual Clock Emulator x
2.10.1. True Dual-Port Mixed Port Read During Write New Data Emulation
3. Agilex™ 5 Embedded Memory Design Considerations x
3.1. Consider the Memory Block Selection 3.2. Consider the Concurrent Write Behavior 3.3. Read-During-Write (RDW) 3.4. Consider Power-Up State and Memory Initialization 3.5. Reduce Power Consumption 3.6. Avoid Providing Non-Deterministic Input 3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously 3.8. Advanced Settings in Quartus® Prime Software for Memory 3.9. Consider the Memory Depth Setting 3.10. Consider Registering the Memory Output
3.3. Read-During-Write (RDW) x
3.3.1. Customize Read-During-Write Behavior
3.3.1. Customize Read-During-Write Behavior x
3.3.1.1. Same-Port Read-During-Write Mode 3.3.1.2. Mixed-Port Read-During-Write Mode 3.3.1.3. Read-During-Write Data Output and Memory Location Behaviors
4. Agilex™ 5 Embedded Memory IP References x
4.1. On-Chip Memory RAM and ROM IPs 4.2. FIFO Intel FPGA IP 4.3. Shift Register (RAM-based) FPGA IP
4.1. On-Chip Memory RAM and ROM IPs x
4.1.1. Release Information for RAM and ROM IPs 4.1.2. Features 4.1.3. Implementation Guide 4.1.4. Parameters and Interface Signals
4.1.2. Features x
4.1.2.1. On-Chip Memory RAM and ROM FPGA IPs
4.1.3. Implementation Guide x
4.1.3.1. Instantiating IP Cores using the Quartus® Prime Parameter Editor
4.1.4. Parameters and Interface Signals x
4.1.4.1. RAM: 1-PORT FPGA IP Parameters 4.1.4.2. RAM: 2-PORT FPGA IP Parameters 4.1.4.3. RAM: 4-PORT FPGA IP Parameters 4.1.4.4. ROM: 1-PORT FPGA IP Parameters 4.1.4.5. ROM: 2-PORT FPGA IP Parameters 4.1.4.6. RAM and ROM Parameter Settings 4.1.4.7. Changing Parameter Settings Manually 4.1.4.8. RAM and ROM Interface Signals
4.2. FIFO Intel FPGA IP x
4.2.1. Release Information for FIFO Intel FPGA IP 4.2.2. Features 4.2.3. Implementation Guide 4.2.4. Parameters and Interface Signals 4.2.5. Design Considerations
4.2.3. Implementation Guide x
4.2.3.1. Instantiating IP Cores using Quartus® Prime Pro Edition Parameter Editor 4.2.3.2. Manual IP Instantiation through HDL
4.2.3.2. Manual IP Instantiation through HDL x
4.2.3.2.1. Verilog HDL Prototype 4.2.3.2.2. VHDL Component Declaration 4.2.3.2.3. VHDL LIBRARY-USE Declaration 4.2.3.2.4. HDL Code from Parameterizable Macros Template 4.2.3.2.5. Coding Example for Manual Instantiation 4.2.3.2.6. Instantiation Template
4.2.4. Parameters and Interface Signals x
4.2.4.1. FIFO Signals 4.2.4.2. FIFO Parameter Settings 4.2.4.3. FIFO Intel FPGA IP Parameters
4.2.5. Design Considerations x
4.2.5.1. FIFO Functional Timing Requirements 4.2.5.2. SCFIFO ALMOST_EMPTY Functional Timing 4.2.5.3. FIFO Output Status Flag and Latency 4.2.5.4. FIFO Metastability Protection and Related Options 4.2.5.5. FIFO Synchronous Clear and Asynchronous Clear Effect 4.2.5.6. SCFIFO and DCFIFO Show-Ahead Mode 4.2.5.7. Different Input and Output Width 4.2.5.8. DCFIFO Timing Constraint Setting 4.2.5.9. Gray-Code Counter Transfer at the Clock Domain Crossing 4.2.5.10. Guidelines for Embedded Memory ECC Feature 4.2.5.11. Reset Scheme
4.2.5.5. FIFO Synchronous Clear and Asynchronous Clear Effect x
4.2.5.5.1. Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO
4.2.5.8. DCFIFO Timing Constraint Setting x
4.2.5.8.1. Embedded Timing Constraint 4.2.5.8.2. User Configurable Timing Constraint
4.2.5.8.2. User Configurable Timing Constraint x
4.2.5.8.2.1. SDC Commands
4.3. Shift Register (RAM-based) FPGA IP x
4.3.1. Release Information for Shift Register (RAM-based) FPGA IP 4.3.2. Features 4.3.3. Implementation Guide 4.3.4. Parameters and Interface Signals
4.3.3. Implementation Guide x
4.3.3.1. Instantiating IP Cores using Quartus® Prime Pro Edition Parameter Editor
4.3.4. Parameters and Interface Signals x
4.3.4.1. Shift Register (RAM-based) FPGA IP Parameter Settings 4.3.4.2. Shift Register Ports and Parameters Setting
1. Agilex™ 5 Embedded Memory Overview
2. Agilex™ 5 Embedded Memory Architecture and Features
3. Agilex™ 5 Embedded Memory Design Considerations
4. Agilex™ 5 Embedded Memory IP References
5. Agilex™ 5 Embedded Memory Debugging
6. Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs Archives
7. Document Revision History for the Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs

4.2.4.3. FIFO Intel FPGA IP Parameters

Table 62.   FIFO Intel FPGA IP Parameters DescriptionThis table lists the parameters for the FIFO IP.
Parameter Legal Values Description
Parameter Settings: Width, Clk, Synchronization
How wide should the FIFO be? — Specifies the width of the data and q ports.
How deep should the FIFO be? Note: You could enter arbitrary values for width 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536, and 131072 Specifies the depth of the FIFO, which is always a power of 2.
Do you want a common clock for reading and writing the FIFO?
  • Yes, synchronize both reading and writing to 'clock'. Create one set of full/empty control signals.
  • No, synchronize reading and writing to 'rdclk' and 'wrclk', respectively. Create a set of full/empty control signals for each clock.
—
Parameter Settings: SCFIFO Options
Would you like to disable any circuitry protection?
  • full
  • empty
  • usedw[] (number of words in FIFO).

    Note: You can use the MSB to generate a half full flag.

  • almost full becomes true when usedw[] is greater than or equal to
  • almost empty becomes true when usedw[] is less than
  • Asynchronous clear
  • Synchronous clear (flush the FIFO)
 On/Off —
Parameter Settings: DCFIFO 1
When you select No, synchronize reading and writing to 'rdclk' and 'wrclk', respectively. Create a set of full/empty control signals for each clock., the following options are available:

Total latency, clock synchronization, metastability protection, area, and fmax options must be set as a group. Total latency is the sum of two write clock rising edges and the number of read clocks selected below.

Which option(s) is most important to the DCFIFO? (Read clk sync stages, metastability protection, area, fmax)

Which type of optimization do you want?
  • Minimal setting for unsynchronized clocks. 2 sync stages, good metastability, medium size, good fmax.
  • Best metastability protection, best fmax, unsynchronized clocks. 3 or more sync stages, best metastability protection, largest size, best fmax.
Specify total latency, clock synchronization, metastability protection, area, and fmax.
  • Minimal setting for unsynchronized clocks—This option uses two synchronization stages with good metastability protection. It uses the medium size and provides good fMAX.
  • Best metastability protection, best fmax, unsynchronized clocks—This option uses three or more synchronization stages with the best metastability protection. It uses the largest size but gives the best fMAX.
More options When you select Best metastability protection, best fmax, unsynchronized clock, the following option is available:
  • How many sync stages?
 3, 4, 5, 6, 7, 8, and 9 Specifies the number synchronization stages.
Timing Constraint
  • Generate SDC file and disable embedded timing constraint
On/Off Generate a SDC file with correct timing constraints. Embedded set_false_path assignment is disabled. The new timing constraints consist of set_net_delay, set_max_skew, set_min_delay and set_max_delay. For more information on the timing constraint usage, refer to user guide.
Parameter Settings: DCFIFO 2
When you select No, synchronize reading and writing to 'rdclk' and 'wrclk', respectively. Create a set of full/empty control signals for each clock., the following options are available:

Which optional output control signals do you want?

usedw[] is the number of words in the FIFO.

 On/Off —
Read-side
  • full
  • empty
  • usedw[]

Note: These signals are synchronous to 'rdclk'.

 —
Write-side
  • full
  • empty
  • usedw[]

Note: These signals are synchronous to 'wrclk'.

 —
More options
  • Add an extra MSB to usedw port(s). Note: You can use the MSB to generate a half-full flag.
  • Asynchronous clear
  • Add circuit to synchronize 'aclr' input with 'wrclk'
  • Add circuit to synchronize 'aclr' input with 'rdclk'
On/Off —
Parameter Settings: Rdreq Option, Blk Type
Which kind of read access do you want with the 'rdreq' signal?
  • Normal FIFO mode.
  • Show-ahead synchronous FIFO mode.
Specifies whether the FIFO is in Legacy mode or in Show-ahead mode.
  • Normal FIFO mode—The data becomes available after 'rdreq is asserted. 'rdreq' acts as a read request.
  • Show-ahead synchronous FIFO mode—The data becomes available before 'rdreq' is asserted. 'rdreq' acts as a read acknowledge. Note: This mode suffers a performance penalty.
What should the memory block type be?
  • Auto
  • MLAB
  • M20K
  • M144K
Specifies the memory block type. The types of memory block that are available for selection depends on your target device.
Set the maximum block depth to: Auto, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536, and 131072 Specifies the maximum block depth in words.
Reduce RAM usage (decreases speed and increases number of Les). Available if data width is divisible by 9. On/Off —
Parameter Settings: Optimization, Circuitry Protection
Would you like to register the output to maximize performance but use more area?
  • Yes (best speed)
  • No (smallest area)
Specifies whether to register the RAM output.
Implement FIFO storage with logic cells only, even if the device contains memory blocks. On/Off Specifies whether to implement FIFO storage with logic cells only.
Would you like to disable any circuitry protection (overflow checking and underflow checking)?
If not required, overflow and underflow checking can be disabled to improve performance.
  • Disable overflow checking. Writing to a full FIFO corrupts contents.
  • Disable underflow checking. Reading from an empty FIFO corrupts contents
 On/Off Specifies whether to disable any circuitry protection for overflow
Would you like to enable ECC?
  • Enable error checking and correcting (ECC)
On/Off Specifies whether to enable error checking and correcting feature.
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