GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 8/07/2024
Public
Document Table of Contents

8.4.2. Debug Registers

The following table lists the debug registers implemented by the GTS AXI Streaming IP. The debug registers starts from Base Address = 0x400.

Table 63.  Debug Register Address Map
Register Name Offset
HIP Status 0X0000_0000
HIP BP CYCLES 0x0000_002C
HIA BP CYCLES 0X0000_0030
APP BP CYCLES 0x0000_003C
HIA RX BP CYCLES 0X0000_0040

Refer to the Excel-based GTS AXI Streaming Intel FPGA IP for PCI Express* Register Map for the detailed descriptions of the registers.