GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 8/07/2024
Public
Document Table of Contents

8.6.1.5. BIST, Header Type, Latency Timer, and Cache Line Size Registers

Address: Offset 0xC

This location contains the BIST, header-type, Latency Timer, and Cache Line Size Registers defined in the PCI 3.0 Specifications. All the fields in this register are hardwired to 0.