Visible to Intel only — GUID: pta1696958329019
Ixiasoft
Visible to Intel only — GUID: pta1696958329019
Ixiasoft
7.8. Control and Status Register Responder Interface
The Control and Status Register Responder interface follows AXI4-Lite protocol, but it does not differentiate between non-secure and secure accesses. All accesses are considered secure. It provides access to PCI/ PCIe* configuration registers of all functions and the IP core registers. You can use this interface to dynamically modify the value of the configuration registers.
Signal Name | Direction | Clock Domain | Description |
---|---|---|---|
Write Address Channel | |||
p<n>_app_ss_lite_csr_awvalid | Input | p<n>_axi_lite_clk | Indicates that the write address channel signals are valid. |
p<n>_ss_app_lite_csr_awready | Output | p<n>_axi_lite_clk | Indicates that a transfer on the write address channel can be accepted. |
p<n>_app_ss_lite_csr_awaddr[19:0] | Input | p<n>_axi_lite_clk | The address of the first transfer in a write transaction. |
Write Data Channel | |||
p<n>_app_ss_lite_csr_wvalid | Input | p<n>_axi_lite_clk | Indicates that the write data channel signals are valid. |
p<n>_ss_app_lite_csr_wready | Output | p<n>_axi_lite_clk | Indicates that a transfer on the write data channel can be accepted. |
p<n>_app_ss_lite_csr_wdata[31:0] | Input | p<n>_axi_lite_clk | Write Data |
p<n>_app_ss_lite_csr_wstrb[3:0] | Input | p<n>_axi_lite_clk | Write strobes, indicate which byte lanes hold valid data. |
Write Response Channel | |||
p<n>_ss_app_lite_csr_bvalid | Output | p<n>_axi_lite_clk | Indicates that the write response channel signals are valid |
p<n>_app_ss_lite_csr_bready | Input | p<n>_axi_lite_clk | Indicates that a transfer on the write response channel can be accepted |
p<n>_ss_app_lite_csr_bresp[1:0] | Output | p<n>_axi_lite_clk | Write response. Indicates the status of a write transaction. |
Read Address Channel | |||
p<n>_app_ss_lite_csr_arvalid | Input | p<n>_axi_lite_clk | Indicates that the read address channel signals are valid. |
p<n>_ss_app_lite_csr_arready | Output | p<n>_axi_lite_clk | Indicates that a transfer on the read address channel can be accepted. |
p<n>_app_ss_lite_csr_araddr[19:0] | Input | p<n>_axi_lite_clk | The address of the first transfer in a read transaction. |
Read Data Channel | |||
p<n>_ss_app_lite_csr_rvalid | Output | p<n>_axi_lite_clk | Indicates that the read data channel signals are valid. |
p<n>_app_ss_lite_csr_rready | Input | p<n>_axi_lite_clk | Indicates that a transfer on the read data channel can be accepted. |
p<n>_ss_app_lite_csr_rdata[32:0] | Output | p<n>_axi_lite_clk | Read data |
p<n>_ss_app_lite_csr_rresp[1:0] | Output | p<n>_axi_lite_clk | Read response, indicates the status of a read transfer. |
For the Physical Function configuration space registers access, your application needs to specify the offsets of the targeted Physical Function registers. For example, if the application wants to read the MSI lower 32-bit message address and upper 32-bit address from MSI Capability Register of Physical Function 0, it issues a read with address 0x80054 to target the MSI Capability Structure of Physical Function 0 followed by another read with address 0x80058.