GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 8/07/2024
Public
Document Table of Contents

8.1. Register Address Map

User application logic can access registers of the GTS AXI Streaming IP as well as HIP physical function (PF) configuration space registers through the AXI4-Lite Control and Status Register Responder interface. The offsets are provided in the following table. The following sections describe the details on the register addresses and bit mappings for each register space.

The Excel-based GTS AXI Streaming IP register map is available for download at GTS AXI Streaming Intel FPGA IP for PCI Express* Register Map .

Table 58.  Address Map offsets through AXI4-Lite Control and Status Register Responder Interface
Offset Registers
0x8_3000 – 0x8_3FFF PF3 PCIe* Configuration Space
0x8_2000 – 0x8_2FFF PF2 PCIe* Configuration Space
0x8_1000 – 0x8_1FFF PF1 PCIe* Configuration Space
0x8_0000 – 0x8_0FFF PF0 PCIe* Configuration Space
0x1_414C – 0x1_415B Root Port Interrupt Status Registers
0x1_41A0 – 0x1_41AF PTM Register
0x0_0800 – 0x0_0BFF Performance Monitor Registers
0x0_0400 – 0x0_07FF Debug Registers
0x0_0000 – 0x0_03FF Control Registers

All AXI-Lite accesses are completed with appropriate response (BRESP, RRESP) so that the bus does not stall.

  • AXI-Lite access to address ranges defined in the Register Address Map must be completed successfully with BRESP/RRESP="OK". This includes access to unimplemented, i.e., Reserved, register offsets within the valid address range.
  • Read to reserved register returns value of all zeroes.
  • Write to register location containing any number of the RO or RO/V bit, the design returns write response BRESP=OKAY. Write is dropped for the RO or RO/V bit location(s). This is not an error condition.
  • AXI-Lite access to address beyond the register map must be completed gracefully with BRESP/RRESP="DECERR". Read returns all zeroes and write is dropped.