Visible to Intel only — GUID: zun1714118805664
Ixiasoft
Visible to Intel only — GUID: zun1714118805664
Ixiasoft
8.6.1.3. Status Registers
Address: Offset 0x6
This address contains the PCI Command and Status Registers.
Bit Location | Description | Attributes | Default |
---|---|---|---|
3:0 | Reserved | RO | 0 |
4 | Indicates the presence of PCI Extended Capabilities. This bit is hardwired to 1. | RO | 1 |
7:5 | Reserved | RO | 0 |
8 | Master Data Parity Error.
The device sets this bit when:
The Parity Error Response enable bit of the PCI Command Register of the parent Physical Function must be set to 1 to enable the setting of this bit. This bit remains 0 when the Parity Error Response enable bit of the parent PF is 0. This bit is cleared by writing a 1 into the bit position. |
RW1C | 0 |
10:9 | Reserved | RO | 0 |
11 | Signaled Target Abort. The device sets this bit when this Virtual Function has sent a Completion to the link with the Completer Abort status. This bit is cleared by writing a 1 into this bit position. |
RW1C | 0 |
12 | Received Target Abort. The device sets this bit when it has received a Completion from the link with the Completer Abort status, directed at this Virtual Function. This bit is cleared by writing a 1 into this bit position. |
RW1C | 0 |
13 | Received Master Abort. The device sets this bit when it has received a Completion from the link with the Unsupported Request (UR) status, targeted at this Virtual Function. This bit is cleared by writing a 1 into this bit position. |
RW1C | 0 |
14 | Signaled System Error. The Virtual Function sets this bit when it has sent out a Fatal or Non-Fatal error message on the link to the Root Complex. The SERR Enable bit of the PCI Command Register of the parent Physical Function must be set to enable the setting of this bit. This bit is cleared by writing a 1 into this bit position. |
RW1C | 0 |
15 | Detected Parity Error. The Virtual Function sets this bit when it has received a Poisoned TLP from the link. This bit is cleared by writing a 1 into this bit position. |
RW1C | 0 |