GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 8/07/2024
Public
Document Table of Contents

8.6.1.4. Revision ID and Class Code Register

Address: Offset 0x8

This register contains the Revision ID and Class Code associated with the device. This register has the same setting as that of parent Physical Function.

Table 68.  Revision ID and Class Code Register Description
Bit Location Description Attributes Default
7:0 Revision number assigned by the manufacturer of the device. RO Programmable
15:8 Programming Interface Byte: Identifies the register set layout of the device. RO Same as parent PF
23:16

Subclass Code.

Identifies a sub-category of the device within the selected Class Code.

RO Same as parent PF
31:24

Class Code.

Identifies the function of the device.

RO Same as parent PF