GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 8/07/2024
Public
Document Table of Contents

8.4.3. Performance Monitor Registers

The following table lists the performance registers implemented by the GTS AXI Streaming IP. The performance monitor registers starts from Base Address = 0x800.

Table 64.   Performance Register Address Map
Register Name Offset
PERFMON CTRL 0X0000_0000
TX MRD TLP 0X0000_0004
TX MWR TLP 0X0000_0008
TX MSG TLP 0X0000_000C
TX CFGWR TLP 0X0000_0010
TX CFGRD TLP 0X0000_0014
RX MRD TLP 0X0000_0018
RX MWR TLP 0X0000_001C
RX MSG TLP 0X0000_0020
RX CFGWR TLP 0X0000_0024
RX CFGRD TLP 0X0000_0028
TX MEM DATA 0X0000_002C
TX CPL DATA 0X0000_0030
RX MEM DATA 0X0000_0034
RX CPL DATA 0X0000_0038

Refer to the Excel-based GTS AXI Streaming Intel FPGA IP for PCI Express* Register Map for the detailed descriptions of the registers.