GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 8/07/2024
Public
Document Table of Contents

8.6.3.1. MSI-X Control Register

Address: Offset 0x0

This register contains the MSIX Capability ID, Capability Pointer, and enable/mask bits. The various fields of the register are described below.

Table 77.  MSI-X Control Register Description
Bit Location Description Attributes Default
31

MSIX Enable.

This bit must be set to enable the MSIX interrupt generation.

You must obtain this information from the configuration intercept interface.

RW 0
30

MSIX Function Mask.

This bit can be set to mask all MSIX interrupts from this Function.

You must obtain this information from the configuration intercept interface.

RW 0
29:27 Reserved RO 0
26:16

Size of the MSI-X Table (number of MSIX interrupt vectors). The value in this field is one less than the size of the table set up for this Function. Maximum value is 0x7FF (2048 interrupt vectors).

This field is shared among all VFs attached to one PF.

RO Programmable
15:8

Next Capability Pointer.

Points to PCI Express Capability.

RO Programmable
7:0 Capability ID assigned by PCI-SIG. RO Same as parent PF