GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 8/07/2024
Public
Document Table of Contents

8.6.2.9. Link Control and Status 2 Register

Address: Offset 0x30

This register contains control and status bits for the PCI Express* link.

Table 76.  Link Control and Status 2 Register Description
Bit Location Description Attributes Default
15:0 Reserved RO 0
16 Current De-emphasis Level. RsvdZ 0
31:17 Reserved RO 0