GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 8/07/2024
Public
Document Table of Contents

8.2.1. PCI Express* Configuration Header Registers

The corresponding section in PCIe* Specification column in the tables in this section list the appropriate sections of the PCI Express* Base Specification that describe these registers.

Figure 62.  PCIe* Type 0 Configuration Space Registers—Byte Address Offsets and Layout
Figure 63.  PCIe* Type 1 Configuration Space Registers—Byte Address Offsets and Layout