Ethernet Subsystem Intel® FPGA IP User Guide

ID 773413
Date 4/03/2023
Document Table of Contents

4.5.1. TX PTP Classifier

The PTP TX Packet Classifier required for IEEE 1588v2 PTP solution design is highlighted in the block diagram of Block Diagram of TX PTP Classifier. This packet classifier is instantiated one instance per each Ethernet port that you select in the Subsystem GUI. The PTP TX Packet Classifier supports static preamble passthrough feature. The preamble feature in PTP TX Packet Classifier is configured during IP generation time and cannot dynamically switch during run time. The PTP TX Packet Classifier in F-Tile can support up to 400G throughput and Multi Packet Mode. For more information on the 1588 Precision Time Protocol Interfaces, refer to Precision Time Protocol in F-Tile Ethernet Intel® FPGA Hard IP User Guide.

IEEE 1588™-2019 defines a network protocol enabling precise synchronization of clocks in measurement and control systems. The Precision Time Protocol (PTP) network protocol defines the mappings to User Datagram Protocol (UDP)/Internet Protocol (IP versions 4 and 6), and layer-2 IEEE 802.3 Ethernet.

The TX PTP classifier detects PTP messages transported over Ethernet, UDP with IPv4 protocol, UDP with IPv6 protocol, with a VLAN tagged, stacked VLAN, untagged, or MPLS encapsulation.

The TX PTP classifier extracts the PTP fields from the PTP header:
  • Message_type[3:0]
  • Message_length[15:0]
  • Two_step_flag

The PTP classifier provides the PTP command generator.

According to the IEEE 1588™-2019 specification, the IPv4 Options field should not be used, and the IPv6 Extension Header is out of scope.

Figure 7. Block Diagram of TX PTP Classifier