Ethernet Subsystem Intel® FPGA IP User Guide

ID 773413
Date 4/03/2023
Document Table of Contents

7.1.20. F-Tile DR Controller Status

Description: F-Tile DR Controller Status register.
Note: Applicable only for F-Tile when DR is enabled.

Byte Offset: 0x118

Addressing Mode: 32 bits

Bit Type Reset Description
31:1 RO 0 Reserved
0 RO 0

0b0 – DR completed successfully, and DR controller is ready.

0b1 – DR is in progress, and DR controller is in use.