Ethernet Subsystem Intel® FPGA IP User Guide

ID 773413
Date 4/03/2023
Document Table of Contents

7.1.2. Device Feature Header Hi

Description: Upper 32-bit of Device Feature Header (DFH)

Byte Offset: 0x4

Addressing Mode: 32 bits

Bit Type Value After Reset Description
31:28 RO 0x3 Feature Type
27:20 RO 0x0 DFH version
19:16 RO 0x0 Feature Minor Revision
15:9 RO 0 Reserved
8:8 RO 0x0 End of List

1’b0= This is last feature header (see “Next DFH Byte Offset”)

7:0 RO 0x00

Next DFH Byte Offset Bit [39:32]

Next DFH Address = 0x00 (Current DFH Address + Next DFH Byte Offset

Used to figure out Next DFH Address and as an indication for the maximum size of MMIO region occupied by this feature.

For last feature, this offset points to the beginning of the unallocated MMIO region, if any (or beyond the end of the MMIO space).