Ethernet Subsystem Intel® FPGA IP User Guide

ID 773413
Date 4/03/2023
Document Table of Contents

6.4. Clock Connections for SyncE Operation on E-Tile

The following figure shows an alternate clocking arrangement for the transceiver clocks that can be used to enable SyncE operation on E-Tile.
Figure 13. Alternate Clock Connections for SyncE Operation on E-Tile

From the figure, it is important to note:

  • Two or more ports can share the clock output of an Off-chip Cleanup PLL that meets the specification for a SyncE link.
  • The FPGA provides a Primary SyncE clock and a backup SyncE clock to the cleanup PLL.
  • The Primary and backup cleanup clocks come from recovered clock output pins from a pair of ports that are both connected to remote stations connected to the same SyncE network, with the transceiver reference clock sourced from the output of the cleanup PLL.
  • In the above figure, o_p<n>_clk_rec_div64 is used; o_p<n>_clk_rec_div can also be used.
  • You must note if the EHIP System clock is derived from a different reference clock than the transceiver, then the IP must be set to Custom Cadence mode to match the PPM difference between the clocks.
  • SyncE clocking can be combined with the datapath clocking schemes shown in the previous sections.
Note: The Ethernet ports do not have to be part of the same instance of the core, or variant.