Ethernet Subsystem Intel® FPGA IP User Guide

ID 773413
Date 4/03/2023
Document Table of Contents

6.6. F-Tile PMA and FEC Direct PHY IP Clock Output

The Ethernet SS supports six different clock output options from TX and RX that you can use for FPGA core clocking.

Refer to Clocking in F-Tile Architecture and PMA and FEC Direct PHY IP User Guide.