Ethernet Subsystem Intel® FPGA IP User Guide

ID 773413
Date 4/03/2023
Document Table of Contents

6. Recommended Clock Connections

The following figure shows the recommended clocking for each Ethernet Port provided by the core; p<n>_app_ss_st_tx_clk and p<n>_app_ss_st_rx_clk must be driven by the same o_p<n>_clk_pll port.

Figure 9. Recommended Clock Connections for Normal Operation

The Tile Refclk/PLL IP and i_clk_sys is instantiated within HSSI SS and only applicable for F-tile.