Ethernet Subsystem Intel® FPGA IP User Guide

ID 773413
Date 4/03/2023
Document Table of Contents

7.2.1. PTP Packet Classifier Registers

All PTP Packet Classifier Registers are 48-bit packet counters. The counter values are represented in 2 registers: lower 32-bit register and upper 16-bit register. When each counter reaches its maximum value and does not roll over, it becomes frozen.. Writing all 1’s value to the lower 32-bit register clears the entire 48-bit counter.