Ethernet Subsystem Intel® FPGA IP User Guide

ID 773413
Date 4/03/2023
Document Table of Contents

4.2. CSR Address Decoder

There are different AVMM reconfiguration interfaces available for the E-Tile and F-Tile Ethernet and PMA/FEC/PCS Direct IP. Each of these interfaces is responsible for accessing various register groups within the transceiver, as well as the soft logic registers within the various IPs of the Subsystem. When you request CSR access via the AXI-Lite interface, the request is internally translated to the AVMM protocol and the request address is decoded based upon the address range defined for each reconfiguration AVMM interface. The address decoder is product and profile specific, and it will finally route the request to the relevant target reconfiguration interface.

Since the AXI-Lite supports byte addressing and F-Tile reconfiguration AVMM interfaces support write byte enable, the incoming AXI-Lite read/write address is decoded and mapped directly to the request of the E-Tile/F-Tile Transceiver Reconfiguration AVMM interface. The Ethernet Subsystem AXI-Lite interface does not support unaligned access, and any requests that includes unaligned access are translated to fully aligned access, ignoring the lower 2 address bits on the request.