Ethernet Subsystem Intel® FPGA IP User Guide

ID 773413
Date 4/03/2023
Public

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Document Table of Contents

7.1.15. Priority Flow Control

Description: PFC Control parameters

Byte Offset: 0x4000 + 0x200 x (0 - 19)

Addressing Mode: 32 bits

Bit Type Reset Description
31:5 RO 0 Reserved
5 RW 0 1'b0 – Normal

1'b1 – Clear RX packet statistics

4 RW 0 1'b0 – Normal

1'b1 – Clear TX packet statistics

3 RW FLOW_CONTROL_EN cfg_flow_control_en: Enable Flow Control

1'b1 – Flow control enabled (PFC or PAUSE – determined by CFG_PFC_SEL)

1'b0 – Flow control disabled, no PFC or PAUSE generation

A switch may cause packet dropping or mixing for a brief time (Maximum of number of queue entries * 8 cycles).
  • After power on, value is set to 1
  • After subsytem_cold_reset_n, the value is set based on the module parameter PORT<X>_FLOW_CONTROL_EN
2:2 RW 0 cfg_pfc_sel: Select between Priority Flow control vs Standard Flow Control (Pause), valid only when CFG_FLOW_CONTROL_EN is set to 1’b1.

1’b1 – PFC is enabled. tx_pfc[7:0] will be generated, rx_pfc[7:0] will be consumed

1’b0 – SFC is enabled. tx_pause will be generated, rx_pause will be consumed

A switch may cause packet dropping or mixing for a brief time (Maximum of number of queue entries * 8 cycles).

1:1 RW 0

Indicate PFC RX queue arbiration scheme.

1’b1 – Priority arbitration priority order (queue 7 - queue 0)

1’b0 – Round-robin arbitration

0:0 RW 0

Indicate PFC TX queue arbiration scheme.

1’b1 – Priority arbitration priority order (queue 7 - queue 0)

1’b0 – Round-robin arbitration