Ethernet Subsystem Intel® FPGA IP User Guide

ID 773413
Date 4/03/2023
Document Table of Contents

7.5. F-Tile PTP Tile Adapter Register Map

The PTP Tile Adapter CSRs are mapped to the subsystem CSR space.
Table 54.  F-Tile PTP Tile Adapter Register Addresses
Reconfiguration Interface Address
PTP Asymmetry Byte Offset: 0x20000 - 0x3FFFF
PTP Peer-to-Peer MeanPathDelay Byte Offset: 0x40000 - 0x5FFFF