External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

ID 772538
Date 3/31/2025
Public
Document Table of Contents

11.10.2.2. Verifying Memory Timing Parameters

Review and update the memory timing parameters, CAS, and Write CAS latency based on the speed bin of the targeted memory component and the operating frequency of your interface.

Incorrect memory timing parameters, CAS, or Write CAS latency can cause data corruption in the memory component.