Visible to Intel only — GUID: cco1742241085247
Ixiasoft
- 4.1.2. s0_axi4_clock_out for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component
- 4.3.2. s0_axi4_clock_out for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component
Visible to Intel only — GUID: cco1742241085247
Ixiasoft
12.1.7.1.1. mb_iossm_command.tcl
The following table lists the mailbox access script functions. (For detailed information on the corresponding arguments for these functions, refer to the subsequent User Input Arguments Description table.)
Registers | Functions | Argumentss |
---|---|---|
MAILBOX_HEADER MEM_INTF_INFO_0 MEM_INTF_INFO_1 MEM_TECHNOLOGY_INTF0 MEM_TECHNOLOGY_INTF1 MEMCLK_FREQ_INTF0 MEMCLK_FREQ_INTF1 MEMCLK_FREQ_FSP0_INTF0 MEMCLK_FREQ_FSP0_INTF1 MEMCLK_FREQ_FSP1_INTF0 MEMCLK_FREQ_FSP1_INTF1 MEMCLK_FREQ_FSP2_INTF0 MEMCLK_FREQ_FSP2_INTF1 MEM_WIDTH_INFO_INTF0 MEM_WIDTH_INFO_INTF1 MEM_TOTAL_CAPACITY_INTF0 MEM_TOTAL_CAPACITY_INTF1 |
intf_info | <calibration interface> |
STATUS STATUS_CAL_INTF0 STATUS_CAL_INTF1 |
cal_status | <calibration interface> |
ECC_ENABLE_INTF0 ECC_ENABLE_INTF1 ECC_SCRUB_STATUS_INTF0 ECC_SCRUB_STATUS_INTF1 |
ecc_status | <calibration interface> |
MEM_INIT_STATUS_INTF0 MEM_INIT_STATUS_INTF1 BIST_STATUS_INTF0 BIST_STATUS_INTF1 |
bist_status | <calibration interface> |
LP_MODE_INTF0 LP_MODE_INTF1 |
lp_mode_status | <calibration interface> |
ECC_ENABLE_SET | mb_ecc_enable_set | <calibration interface> <CMD_TARGET_IP_TYPE> <CMD_TARGET_IP_INSTANCE_ID> <ECC_ENABLE> |
ECC_INTERRUPT_MASK | mb_ecc_interrupt_mask | <calibration interface> <CMD_TARGET_IP_TYPE> <CMD_TARGET_IP_INSTANCE_ID> <ECC_INTERRUPT_MASK> |
ECC_WRITEBACK_ENABLE | mb_ecc_writeback_enable | <calibration interface> <CMD_TARGET_IP_TYPE> <CMD_TARGET_IP_INSTANCE_ID> <ECC_WRITEBACK_EN> |
ECC_INJECT_ERROR | mb_ecc_inject_error | <calibration interface> <CMD_TARGET_IP_TYPE> <CMD_TARGET_IP_INSTANCE_ID> <ECC_XOR_CHECK_BITS> |
ECC_CLEAR_ERR_BUFFER | mb_ecc_clear_buffer | <calibration interface> <CMD_TARGET_IP_TYPE> <CMD_TARGET_IP_INSTANCE_ID> |
ECC_SCRUB_MODE_0_START | mb_ecc_scrub_mode_0_start | <calibration interface> <CMD_TARGET_IP_TYPE> <ECC_SCRUB_INTERVAL> <ECC_SCRUB_LEN> <ECC_SCRUB_FULL_MEM> <ECC_SCRUB_START_ADDR [31:0]> <ECC_SCRUB_START_ADDR [36:32]> <ECC_SCRUB_END_ADDR [31:0]> <ECC_SCRUB_END_ADDR [36:32]> |
ECC_SCRUB_MODE_1_START | mb_ecc_scrub_mode_1_start | <calibration interface> <CMD_TARGET_IP_TYPE> <ECC_SCRUB_IDLE_CNT> <ECC_SCRUB_LEN> <ECC_SCRUB_FULL_MEM> <ECC_SCRUB_START_ADDR [31:0]> <ECC_SCRUB_START_ADDR [36:32]> <ECC_SCRUB_END_ADDR [31:0]> <ECC_SCRUB_END_ADDR [36:32]> |
BIST_STANDARD_MODE_START | mb_run_bist_std_mode_start | <calibration interface> <CMD_TARGET_IP_TYPE> <CMD_TARGET_IP_INSTANCE_ID> <BIST_ADDR_SPACE [5:0]> |
BIST_MEM_INIT_START | mb_bist_mem_init_start | <calibration interface> <CMD_TARGET_IP_TYPE> <CMD_TARGET_IP_INSTANCE_ID> <BIST_DATA_PATTERN> <BIST_START_ADDR [37:32]> <BIST_START_ADDR [31:0]> <BIST_FULL_MEM> |
BIST_SET_DATA_PATTERN_UPPER | mb_bist_set_data_pattern_upper | <calibration interface> <CMD_TARGET_IP_TYPE> <CMD_TARGET_IP_INSTANCE_ID> <BIST_DATA_PATTERN [287:256]> <BIST_DATA_PATTERN [255:224]> <BIST_DATA_PATTERN [223:192]> <BIST_DATA_PATTERN [191:160]> |
BIST_SET_DATA_PATTERN_LOWER | mb_bist_set_data_pattern_lower | <calibration interface> <CMD_TARGET_IP_TYPE> <CMD_TARGET_IP_INSTANCE_ID> <BIST_DATA_PATTERN [159:128]> <BIST_DATA_PATTERN [127:96]> <BIST_DATA_PATTERN [95:64]> <BIST_DATA_PATTERN [63:32]> <BIST_DATA_PATTERN [31:0]> |
CHANGE_FSP_LP5 | mb_change_fsp_lp5 | <calibration interface> <CMD_TARGET_IP_TYPE> <CMD_TARGET_IP_INSTANCE_ID> <TARGET_FSP> |
LP_MODE_ENTER | mb_lp_mode_enter | <calibration interface> <CMD_TARGET_IP_TYPE> <CMD_TARGET_IP_INSTANCE_ID> <LP_STATE> |
LP_MODE_EXIT | mb_lp_mode_exit | <calibration interface> <CMD_TARGET_IP_TYPE> <CMD_TARGET_IP_INSTANCE_ID> |
LP_MODE_AUTO | mb_lp_mode_auto | <calibration interface> <CMD_TARGET_IP_TYPE> <CMD_TARGET_IP_INSTANCE_ID> <LP_STATE_AUTO> <LP_IDLE_CNT> |
TRIG_MEM_CAL | mb_reset_cal | <calibration interface> <CMD_TARGET_IP_TYPE> <CMD_TARGET_IP_INSTANCE_ID> |
Arguments | Valid Input | Description |
---|---|---|
<calibration interface> | calip_0 | Calibration interface instance 0 |
calip_1 | Calibration interface instance 1 | |
<CMD_TARGET_IP_TYPE> | 0x1, 0x2, 0x3, 0x4 | Refer to the CMD_REQ Definition table. |
<CMD_TARGET_IP_INSTANCE_ID> | Unique ID defined in EMIF IP | Refer to the CMD_REQ Definition table. |
<ECC_ENABLE> | 0x0, 0x1, 0x2, 0x3 | Refer to the ECC_ENABLE_SET description in the Command Definitions table. |
<ECC_INTERRUPT_MASK> | 0x0 – 0xfff | Refer to the ECC_INTERRUPT_MASK description in the Command Definitions table. |
<ECC_WRITEBACK_EN> | 0x0, 0x1 | Refer to the ECC_WRITEBACK_EN description in the Command Definitions table. |
<ECC_XOR_CHECK_BITS> | Refer table 283 | Refer to the ECC_INJECT_ERROR description in the Command Definitions table. |
<ECC_SCRUB_INTERVAL> | User defined | Refer to the ECC_SCRUB_MODE_0_START description in the Command Definitions table. |
<ECC_SCRUB_LEN> | 0x8, 0x10 | |
<ECC_SCRUB_FULL_MEM> | 0x0, 0x1 | |
<ECC_SCRUB_START_ADDR [31:0]> <ECC_SCRUB_START_ADDR [36:32]> |
User defined | |
<ECC_SCRUB_END_ADDR [31:0]> <ECC_SCRUB_END_ADDR [36:32]> |
User defined | |
<ECC_SCRUB_IDLE_CNT> | User defined | Refer to the ECC_SCRUB_MODE_1_START description in the Command Definitions table. |
<BIST_ADDR_SPACE [5:0]> | User defined | Refer to the BIST_STANDARD_MODE_START description in the Command Definitions table. |
<BIST_DATA_PATTERN> | 0x0, 0x1 | Refer to the BIST_MEM_INIT_START description in the Command Definitions table. |
<BIST_START_ADDR [37:32]> <BIST_START_ADDR [31:0]> |
User defined | Refer to the BIST_MEM_INIT_START description in the Command Definitions table. |
<BIST_FULL_MEM> | 0x0, 0x1 | Refer to the BIST_MEM_INIT_START description in the Command Definitions table. |
<BIST_DATA_PATTERN [287:256]> <BIST_DATA_PATTERN [255:224]> <BIST_DATA_PATTERN [223:192]> <BIST_DATA_PATTERN [191:160]> |
User defined | Refer to the BIST_SET_DATA_PATTERN_UPPER description in the Command Definitions table. |
<BIST_DATA_PATTERN [159:128]> <BIST_DATA_PATTERN [127:96]> <BIST_DATA_PATTERN [95:64]> <BIST_DATA_PATTERN [63:32]> <BIST_DATA_PATTERN [31:0]> |
User defined | Refer to the BIST_SET_DATA_PATTERN_LOWER description in the Command Definitions table. |
<TARGET_FSP> | 0x0, 0x1, 0x2 | Refer to the CHANGE_FSP_LP5 description in the Command Definitions table. |
<LP_STATE> | 0x8, 0x9, 0xa, 0xd, 0xe, 0xf | Refer to the LP_MODE_ENTER description in the Command Definitions table. |
<LP_STATE_AUTO> | 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0xb, 0xc | Refer to the LP_MODE_AUTO description in the Command Definitions table. |
<LP_IDLE_CNT> | User defined |