External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

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ID 772538
Date 3/31/2025
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Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP 2. Agilex™ 7 M-Series FPGA EMIF IP – Introduction 3. Agilex™ 7 M-Series FPGA EMIF IP – Product Architecture 4. Agilex™ 7 M-Series FPGA EMIF IP – End-User Signals 5. Agilex™ 7 M-Series FPGA EMIF IP – Simulating Memory IP 6. Agilex™ 7 M-Series FPGA EMIF IP – DDR4 Support 7. Agilex™ 7 M-Series FPGA EMIF IP – DDR5 Support 8. Agilex™ 7 M-Series FPGA EMIF IP – LPDDR5 Support 9. Agilex™ 7 M-Series FPGA EMIF IP – Timing Closure 10. Agilex™ 7 M-Series FPGA EMIF IP – Controller Optimization 11. Agilex™ 7 M-Series FPGA EMIF IP – Debugging 12. Agilex™ 7 FPGA EMIF IP - Mailbox Support 13. Document Revision History for External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP x
1.1. Release Information
2. Agilex™ 7 M-Series FPGA EMIF IP – Introduction x
2.1. Agilex™ 7 M-Series EMIF IP Protocol and Feature Support 2.2. Agilex™ 7 M-Series EMIF IP Design Flow 2.3. Agilex™ 7 M-Series EMIF IP Design Checklist
3. Agilex™ 7 M-Series FPGA EMIF IP – Product Architecture x
3.1. Agilex™ 7 M-Series EMIF Architecture: Introduction 3.2. Agilex™ 7 M-Series EMIF Sequencer 3.3. Agilex™ 7 M-Series EMIF Controller 3.4. Agilex™ 7 M-Series EMIF IP Interface Protocol: Interface Width, User Access Mode, and ECC 3.5. Agilex™ 7 M-Series EMIF IP for Hard Processor Subsystem (HPS)
3.1. Agilex™ 7 M-Series EMIF Architecture: Introduction x
3.1.1. Agilex™ 7 M-Series EMIF Architecture: I/O Subsystem 3.1.2. Agilex™ 7 M-Series EMIF Architecture: I/O SSM 3.1.3. Agilex™ 7 M-Series EMIF Architecture: I/O Bank 3.1.4. Agilex™ 7 M-Series EMIF Architecture: I/O Lane 3.1.5. Agilex™ 7 M-Series EMIF Architecture: Input DQS Clock Tree 3.1.6. Agilex™ 7 M-Series EMIF Architecture: PHY Clock Tree 3.1.7. Agilex™ 7 M-Series EMIF Architecture: PLL Reference Clock Networks 3.1.8. Agilex™ 7 M-Series EMIF Architecture: Clock Phase Alignment 3.1.9. User Clock in Different Core Access Modes
3.1.3. Agilex™ 7 M-Series EMIF Architecture: I/O Bank x
3.1.3.1. I/O Byte Lane Organization in Different Agilex™ 7 M-Series Devices 3.1.3.2. Lockstep Configuration 3.1.3.3. DDR4 Pin Placement 3.1.3.4. DDR5 Pin Placement 3.1.3.5. LPDDR5 Pin Placement 3.1.3.6. I/O Sub-Bank Usage
3.3. Agilex™ 7 M-Series EMIF Controller x
3.3.1. Hard Memory Controller
3.3.1. Hard Memory Controller x
3.3.1.1. Hard Memory Controller Features
3.5. Agilex™ 7 M-Series EMIF IP for Hard Processor Subsystem (HPS) x
3.5.1. Restrictions on I/O Bank Usage for Agilex™ 7 M-Series EMIF IP with HPS
3.5.1. Restrictions on I/O Bank Usage for Agilex™ 7 M-Series EMIF IP with HPS x
3.5.1.1. Using the Legacy EMIF Debug Toolkit with Agilex™ 7 M-Series HPS Interfaces
4. Agilex™ 7 M-Series FPGA EMIF IP – End-User Signals x
4.1. IP Interfaces for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.2. IP Interfaces for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.3. IP Interfaces for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.4. IP Interfaces for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.5. IP Interfaces for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5
4.1. IP Interfaces for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component x
4.1.1. s0_axi4_clock_in for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.2. s0_axi4_clock_out for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.3. s0_axi4_ctrl_ready for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.4. core_init_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.5. s0_axi4 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.6. s0_axi4lite_clock for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.7. s0_axi4lite_reset_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.8. s0_axi4lite for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.9. mem_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.10. mem_ck_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.11. mem_reset_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.12. oct_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.13. ref_clk for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component
4.2. IP Interfaces for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM x
4.2.1. s0_axi4_clock_in for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.2. s0_axi4_clock_out for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.3. s0_axi4_ctrl_ready for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.4. core_init_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.5. s0_axi4 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.6. s0_axi4lite_clock for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.7. s0_axi4lite_reset_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.8. s0_axi4lite for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.9. mem_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.10. mem_ck_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.11. mem_reset_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.12. oct_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.13. ref_clk for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM
4.3. IP Interfaces for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component x
4.3.1. s0_axi4_clock_in for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.2. s0_axi4_clock_out for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.3. s0_axi4_ctrl_ready for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.4. core_init_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.5. s0_axi4 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.6. s1_axi4 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.7. s0_axi4lite_clock for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.8. s0_axi4lite_reset_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.9. s0_axi4lite for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.10. mem_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.11. mem_ck_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.12. mem_reset_n_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.13. mem_1 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.14. mem_ck_1 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.15. mem_reset_n_1 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.16. oct_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.17. oct_1 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.18. ref_clk for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component
4.4. IP Interfaces for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM x
4.4.1. s0_axi4_clock_out for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.2. s0_axi4_ctrl_ready for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.3. s1_axi4_clock_out for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.4. s1_axi4_ctrl_ready for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.5. s0_axi4_clock_in for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.6. core_init_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.7. s0_axi4 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.8. s1_axi4 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.9. s0_axi4lite_clock for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.10. s0_axi4lite_reset_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.11. s0_axi4lite for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.12. s1_axi4lite_clock for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.13. s1_axi4lite_reset_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.14. s1_axi4lite for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.15. mem_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.16. mem_1 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.17. mem_reset_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.18. mem_ck_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.19. mem_ck_1 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.20. mem_i3c for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.21. mem_lb_dq for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.22. mem_lb_dqs for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.23. oct_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.24. oct_1 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.25. ref_clk for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM
4.5. IP Interfaces for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 x
4.5.1. s0_axi4_clock_in for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.2. core_init_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.3. s0_axi4_ctrl_ready for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.4. s0_axi4_clock_out for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.5. s1_axi4_ctrl_ready for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.6. s1_axi4_clock_out for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.7. s0_axi4 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.8. s1_axi4 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.9. s2_axi4 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.10. s3_axi4 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.11. s0_axi4lite_clock for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.12. s0_axi4lite_reset_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.13. s0_axi4lite for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.14. s1_axi4lite_clock for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.15. s1_axi4lite_reset_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.16. s1_axi4lite for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.17. mem_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.18. mem_ck_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.19. mem_1 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.20. mem_ck_1 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.21. mem_2 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.22. mem_ck_2 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.23. mem_3 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.24. mem_ck_3 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.25. mem_reset_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.26. oct_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.27. oct_1 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.28. oct_2 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.29. oct_3 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.30. ref_clk for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5
5. Agilex™ 7 M-Series FPGA EMIF IP – Simulating Memory IP x
5.1. Simulation Walkthrough
5.1. Simulation Walkthrough x
5.1.1. Calibration 5.1.2. Simulation Scripts 5.1.3. Functional Simulation with Verilog HDL 5.1.4. Simulating the Design Example
6. Agilex™ 7 M-Series FPGA EMIF IP – DDR4 Support x
6.1. External Memory Interfaces (EMIF) IP - DDR4 Component Parameter Descriptions 6.2. External Memory Interfaces (EMIF) IP - DDR4 DIMM Parameter Descriptions 6.3. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning 6.4. DDR4 Board Design Guidelines
6.3. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning x
6.3.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins 6.3.2. Agilex™ 7 M-Series FPGA EMIF IP Resources 6.3.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP 6.3.4. Pin Placements for Agilex™ 7 M-Series FPGA DDR4 EMIF IP
6.3.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins x
6.3.1.1. Estimating Pin Requirements 6.3.1.2. DIMM Options 6.3.1.3. Maximum Number of Interfaces
6.3.2. Agilex™ 7 M-Series FPGA EMIF IP Resources x
6.3.2.1. OCT 6.3.2.2. PLL
6.3.4. Pin Placements for Agilex™ 7 M-Series FPGA DDR4 EMIF IP x
6.3.4.1. Address and Command Pin Placement for DDR4 6.3.4.2. DDR4 Data Width Mapping 6.3.4.3. General Guidelines - DDR4 6.3.4.4. x4 DIMM Implementation 6.3.4.5. Specific Pin Connection Requirements 6.3.4.6. Command and Address Signals 6.3.4.7. Clock Signals 6.3.4.8. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.4. DDR4 Board Design Guidelines x
6.4.1. Terminations for DDR4 with Agilex™ 7 M-Series Devices 6.4.2. General Layout Routing Guidelines 6.4.3. Reference Stackup 6.4.4. Agilex™ 7 M-Series EMIF-Specific Routing Guidelines for Various DDR4 Topologies 6.4.5. DDR4 Routing Guidelines: Discrete (Component) Topologies
6.4.1. Terminations for DDR4 with Agilex™ 7 M-Series Devices x
6.4.1.1. Dynamic On-Chip Termination (OCT) 6.4.1.2. Dynamic On-Die Termination (ODT) in DDR4 6.4.1.3. Choosing Terminations on Agilex™ 7 M-Series FPGA Devices 6.4.1.4. On-Chip Termination Recommendations for Agilex™ 7 M-Series FPGA Devices
6.4.4. Agilex™ 7 M-Series EMIF-Specific Routing Guidelines for Various DDR4 Topologies x
6.4.4.1. One DIMM per Channel (1DPC) for UDIMM, RDIMM, and SODIMM DDR4 Topologies 6.4.4.2. Skew Matching Guidelines for DIMM Configurations 6.4.4.3. Power Delivery Recommendations for the Memory / DIMM Side
6.4.5. DDR4 Routing Guidelines: Discrete (Component) Topologies x
6.4.5.1. Single Rank and Dual Rank x 8 Discrete (Component) Topology 6.4.5.2. Single Rank x16 and Dual Rank x16 Discrete (Component) Topology 6.4.5.3. ADDR/CMD Reference Voltage/RESET Signal Routing Guidelines for Single Rank x 8 and Single Rank x 16 Discrete (Component) Topologies 6.4.5.4. Skew Matching Guidelines for DDR4 Discrete Configurations 6.4.5.5. Power Delivery Recommendations for DDR4 Discrete Configurations 6.4.5.6. Agilex™ 7 M-Series EMIF Pin Swapping Guidelines
6.4.5.6. Agilex™ 7 M-Series EMIF Pin Swapping Guidelines x
6.4.5.6.1. DDR4 Byte Lane Swapping 6.4.5.6.2. DDR4 Address and Command and CLK Lane 6.4.5.6.3. DDR4 Interface x8 Data Lane 6.4.5.6.4. DDR4 Interface x4 Data Lane 6.4.5.6.5. Pin Swizzling
7. Agilex™ 7 M-Series FPGA EMIF IP – DDR5 Support x
7.1. External Memory Interfaces (EMIF) IP - DDR5 Component Parameter Descriptions 7.2. External Memory Interfaces (EMIF) IP - DDR5 DIMM Parameter Descriptions 7.3. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning 7.4. DDR5 Board Design Guidelines
7.3. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning x
7.3.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins 7.3.2. Agilex™ 7 M-Series FPGA EMIF IP Resources 7.3.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP 7.3.4. Pin Placements for Agilex™ 7 M-Series FPGA DDR5 EMIF IP 7.3.5. Agilex™ 7 M-Series EMIF Pin Swapping Guidelines
7.3.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins x
7.3.1.1. Estimating Pin Requirements 7.3.1.2. DIMM Options 7.3.1.3. Maximum Number of Interfaces
7.3.2. Agilex™ 7 M-Series FPGA EMIF IP Resources x
7.3.2.1. OCT 7.3.2.2. PLL
7.3.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP x
7.3.3.1. General Guidelines - DDR5 7.3.3.2. x4 DIMM Implementation 7.3.3.3. Specific Pin Connection Requirements 7.3.3.4. Command and Address Signals 7.3.3.5. Clock Signals 7.3.3.6. Data, Data Strobes, DM, and Optional ECC Signals
7.3.4. Pin Placements for Agilex™ 7 M-Series FPGA DDR5 EMIF IP x
7.3.4.1. Address and Command Pin Placement for DDR5 7.3.4.2. DDR5 Data Width Mapping
7.3.5. Agilex™ 7 M-Series EMIF Pin Swapping Guidelines x
7.3.5.1. DDR5 Byte Lane Swapping 7.3.5.2. DDR5 Address and Command and CLK Lane 7.3.5.3. DDR5 Interface x8 Data Lane 7.3.5.4. DDR5 Interface x4 Data Lane 7.3.5.5. Pin Swizzling
7.4. DDR5 Board Design Guidelines x
7.4.1. PCB Stack-up and Design Considerations 7.4.2. General Design Considerations 7.4.3. DDR Differential Signals Routing 7.4.4. Ground Plane and Return Path 7.4.5. RDIMM, UDIMM, and SODIMM Break-in Layout Guidelines 7.4.6. DRAM Break-in Layout Guidelines 7.4.7. General Notes for EMIF Routing Guidelines Tables 7.4.8. DDR5 PCB Layout Guidelines 7.4.9. DDR5 RDIMM Power Management IC 7.4.10. DDR5 Simulation Strategy
7.4.8. DDR5 PCB Layout Guidelines x
7.4.8.1. DDR5 Discrete Component/Memory Down Topology: Single Rank x8 or x16, Dual Rank x8 or x16 7.4.8.2. Routing Guidelines for DDR5 Memory Down: Single Rank or Dual Rank (x8 bit or x16 bit) Configurations 7.4.8.3. Routing Guidelines for DDR5 RDIMM, UDIMM, and SODIMM Configurations 7.4.8.4. Example of a DDR5 layout on an Altera FPGA Platform Board
8. Agilex™ 7 M-Series FPGA EMIF IP – LPDDR5 Support x
8.1. External Memory Interfaces (EMIF) IP - LPDDR5 Parameter Descriptions 8.2. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning 8.3. LPDDR5 Board Design Guidelines
8.2. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning x
8.2.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins 8.2.2. Agilex™ 7 M-Series FPGA EMIF IP Resources 8.2.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP 8.2.4. Pin Placements for Agilex™ 7 M-Series FPGA LPDDR5 EMIF IP
8.2.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins x
8.2.1.1. Estimating Pin Requirements 8.2.1.2. LPDDR5 Component Options 8.2.1.3. Maximum Number of Interfaces
8.2.2. Agilex™ 7 M-Series FPGA EMIF IP Resources x
8.2.2.1. OCT 8.2.2.2. PLL
8.2.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP x
8.2.3.1. General Guidelines - LPDDR5 8.2.3.2. Specific Pin Connection Requirements 8.2.3.3. Command and Address Signals 8.2.3.4. Clock Signals
8.2.4. Pin Placements for Agilex™ 7 M-Series FPGA LPDDR5 EMIF IP x
8.2.4.1. Address and Command Pin Placement for LPDDR5 8.2.4.2. LPDDR5 Data Width Mapping 8.2.4.3. LPDDR5 Byte Lane Swapping
8.3. LPDDR5 Board Design Guidelines x
8.3.1. PCB Stack-up and Design Considerations 8.3.2. General Design Considerations 8.3.3. DDR Differential Signals Routing 8.3.4. Ground Plane and Return Path 8.3.5. DRAM Break-in Layout Guidelines 8.3.6. General Notes for EMIF Routing Guidelines Tables 8.3.7. LPDDR5 PCB Layout Guidelines 8.3.8. LPDDR5 Simulation Strategy
8.3.7. LPDDR5 PCB Layout Guidelines x
8.3.7.1. LPDDR5 Discrete Component/Memory Down Topology, Single Rank or Dual Rank 8.3.7.2. Routing Guidelines for LPDDR5 Memory Down Topology 8.3.7.3. Example of an LPDDR5 Layout on an Altera® FPGA Platform Board
9. Agilex™ 7 M-Series FPGA EMIF IP – Timing Closure x
9.1. Timing Closure 9.2. Optimizing Timing
9.1. Timing Closure x
9.1.1. Timing Analysis
9.1.1. Timing Analysis x
9.1.1.1. PHY or Core
10. Agilex™ 7 M-Series FPGA EMIF IP – Controller Optimization x
10.1. mrh_Optimizing Efficiency for Secondary Controller 10.2. Interface Standard 10.3. Bank Management Efficiency 10.4. Data Transfer 10.5. Improving Controller Efficiency
10.5. Improving Controller Efficiency x
10.5.1. Using Multiple AXI IDs 10.5.2. Frequency of Operation 10.5.3. Series of Reads or Writes 10.5.4. AXI to Memory Mapping
11. Agilex™ 7 M-Series FPGA EMIF IP – Debugging x
11.1. Interface Configuration Performance Issues 11.2. Functional Issue Evaluation 11.3. Timing Issue Characteristics 11.4. Verifying Memory IP Using the Signal Tap Logic Analyzer 11.5. Debugging with the External Memory Interface Debug Toolkit 11.6. Generating Traffic with the Test Engine IP 11.7. Guidelines for Developing HDL for Traffic Generator 11.8. Guidelines for Traffic Generator Status Check 11.9. Hardware Debugging Guidelines 11.10. Categorizing Hardware Issues 11.11. Debugging Intermittent Issues
11.1. Interface Configuration Performance Issues x
11.1.1. Interface Configuration Bottleneck and Efficiency Issues
11.2. Functional Issue Evaluation x
11.2.1. Altera IP Memory Model 11.2.2. Vendor Memory Model 11.2.3. Transcript Window Messages
11.3. Timing Issue Characteristics x
11.3.1. Evaluating FPGA Timing Issues 11.3.2. Evaluating External Memory Interface Timing Issues
11.5. Debugging with the External Memory Interface Debug Toolkit x
11.5.1. Prerequisites for Using the EMIF Debug Toolkit 11.5.2. Configuring Your Design to Use the EMIF Debug Toolkit 11.5.3. Launching the EMIF Debug Toolkit 11.5.4. Using the EMIF Debug Toolkit
11.5.4. Using the EMIF Debug Toolkit x
11.5.4.1. Rerunning Calibration 11.5.4.2. Rerunning the Test Engine 11.5.4.3. Saving Debug Print 11.5.4.4. Calibration Reports 11.5.4.5. Driver Margining Tab 11.5.4.6. Pin Delay Settings Tab
11.8. Guidelines for Traffic Generator Status Check x
11.8.1. Status Check Using the Signal Tap Logic Analyzer 11.8.2. Exporting the Status Interface to the Top-Level Design
11.9. Hardware Debugging Guidelines x
11.9.1. Create a Simplified Design that Demonstrates the Same Issue 11.9.2. Measure Power Distribution Network 11.9.3. Measure Signal Integrity and Setup and Hold Margin 11.9.4. Vary Voltage 11.9.5. Operate at a Lower Speed 11.9.6. Determine Whether the Issue Exists in Previous Versions of Software 11.9.7. Determine Whether the Issue Exists in the Current Version of Software 11.9.8. Try A Different PCB 11.9.9. Try Other Configurations 11.9.10. Debugging Checklist
11.10. Categorizing Hardware Issues x
11.10.1. Signal Integrity Issues 11.10.2. Hardware and Calibration Issues
11.10.1. Signal Integrity Issues x
11.10.1.1. Characteristics of Signal Integrity Issues 11.10.1.2. Evaluating Signal Integrity Issues
11.10.1.2. Evaluating Signal Integrity Issues x
11.10.1.2.1. Skew 11.10.1.2.2. Crosstalk 11.10.1.2.3. Power System 11.10.1.2.4. Clock Signals 11.10.1.2.5. Address and Command Signals 11.10.1.2.6. Read Data Valid Window and Eye Diagram 11.10.1.2.7. Write Data Valid Window and Eye Diagram
11.10.2. Hardware and Calibration Issues x
11.10.2.1. Verifying High-Level Configuration 11.10.2.2. Verifying Memory Timing Parameters 11.10.2.3. Verifying the Correct Memory Component or DIMM is Installed
12. Agilex™ 7 FPGA EMIF IP - Mailbox Support x
12.1. Agilex™ 7 Mailbox Structure and Register Definitions
12.1. Agilex™ 7 Mailbox Structure and Register Definitions x
12.1.1. Mailbox Supported Commands Read-Only Registers Mailbox Supported Commands 12.1.2. Mailbox Command Definitions 12.1.3. ECC Syndrome Codes 12.1.4. ECC Error Handling 12.1.5. Accessing Read-Only Registers 12.1.6. Sending a Mailbox Command 12.1.7. IOSSM Mailbox Access Script
12.1.5. Accessing Read-Only Registers x
12.1.5.1. Example 1: Reading IP_TYPE and IP_INSTANCE_ID of All the Interfaces in the IO96B Through Read-Only Registers 12.1.5.2. Example 2: Reading the Memory Clock Frequency for an Interface
12.1.6. Sending a Mailbox Command x
12.1.6.1. Example 3: Sending Recalibration Request and Reading Calibration Status Using the Mailbox
12.1.6.1. Example 3: Sending Recalibration Request and Reading Calibration Status Using the Mailbox x
12.1.6.1.1. Example 4: Sending ECC_INJECT_ERROR Using the Mailbox and Reading ECC Error Status, ECC Error Buffer Registers
12.1.7. IOSSM Mailbox Access Script x
12.1.7.1. Mailbox Script Overview 12.1.7.2. Running the Mailbox Script
12.1.7.1. Mailbox Script Overview x
12.1.7.1.1. mb_iossm_command.tcl 12.1.7.1.2. mb_user_input.tcl
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP
2. Agilex™ 7 M-Series FPGA EMIF IP – Introduction
3. Agilex™ 7 M-Series FPGA EMIF IP – Product Architecture
4. Agilex™ 7 M-Series FPGA EMIF IP – End-User Signals
5. Agilex™ 7 M-Series FPGA EMIF IP – Simulating Memory IP
6. Agilex™ 7 M-Series FPGA EMIF IP – DDR4 Support
7. Agilex™ 7 M-Series FPGA EMIF IP – DDR5 Support
8. Agilex™ 7 M-Series FPGA EMIF IP – LPDDR5 Support
9. Agilex™ 7 M-Series FPGA EMIF IP – Timing Closure
10. Agilex™ 7 M-Series FPGA EMIF IP – Controller Optimization
11. Agilex™ 7 M-Series FPGA EMIF IP – Debugging
12. Agilex™ 7 FPGA EMIF IP - Mailbox Support
13. Document Revision History for External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

12.1.1. Mailbox Supported Commands

Read-Only Registers

The following read-only registers provide direct access to retrieve information. Note that these registers are not write-protected; you should not attempt to write to any of these registers. Additionally, you should avoid reading from registers that are not used in the target design, as doing so might result in unpredictable or invalid data being returned.

Table 240.  Read-Only Registers
Register Name Byte Offset (Hexadecimal) Description
MAILBOX_HEADER 0x000

[Output] Mailbox Header

This register specifies information about the mailbox protocol.

[Fields]

[2:0] MB_SPEC_VER: This field specifies the version of mailbox specification being used by the IOSSM firmware.

Current version number is 1.
MEM_INTF_INFO_0 0x200

[Output] Memory Interface Information

This register specifies the memory interface IP type and instance ID for the interface 0/1 in the IO96B. It will only return the primary interface of each channel.

[Fields]

[31:29] IP_TYPE: Indicates the type of IP:

  • 0x0 – Not used.
  • 0x1 – Primary MC of Primary IO96B.
  • 0x2 – Secondary MC of Primary IO96B.
  • 0x3 – Primary MC of Secondary IO96B.
  • 0x4 – Secondary MC of Secondary IO96B.
[28:24] INSTANCE_ID: IP identifier.
MEM_INTF_INFO_1 0x280
MEM_TECHNOLOGY_INTF0 0x210

[Output] Memory Technology

This register provides the memory technology type for the memory interface 0/1.

[Fields]

[2:0] TECH: Reports the memory technology type:
  • 0x0 = DDR4
  • 0x1 = DDR5
  • 0x2 = DDR5_RDIMM
  • 0x3 = LPDDR4
  • 0x4 = LPDDR5
MEM_TECHNOLOGY_INTF1 0x290
MEMCLK_FREQ_INTF0 0x220

[Output] Memory Clock Frequency - This register reports the memory clock frequency in kilohertz (KHz) for the memory interface 0/1. For protocols with multiple FSPs, it reports the current memory clock frequency in kilohertz (KHz).

[Fields]

[31:0] FREQ_KHZ_FSP_CUR: Current memory clock frequency in KHz.
MEMCLK_FREQ_INTF1 0x2A0
MEMCLK_FREQ_FSP0_INTF0 0x224

[Output] Memory Clock Frequency - Frequency Set Point 0

This register reports the memory clock frequency in kilohertz (KHz) for Frequency Set Point 0 of the memory interface 0/1. Only valid for LPDDR5 protocol.

[Fields]

[31:0] FREQ_KHZ_FSP0: Memory clock frequency in KHz for Frequency Set Point 0.
MEMCLK_FREQ_FSP0_INTF1 0x2A4
MEMCLK_FREQ_FSP1_INTF0 0x228

[Output] Memory Clock Frequency - Frequency Set Point 1

This register reports the memory clock frequency in kilohertz (KHz) for Frequency Set Point 1 of the memory interface 0/1. Only valid for LPDDR5 protocol.

[Fields]

[31:0] FREQ_KHZ_FSP1: Memory clock frequency in KHz for Frequency Set Point 1.
MEMCLK_FREQ_FSP1_INTF1 0x2A8
MEMCLK_FREQ_FSP2_INTF0 0X22C

MEMCLK_FREQ_INTF0_FSP2

[Output] Memory Clock Frequency - Frequency Set Point 2

This register reports the memory clock frequency in kilohertz (KHz) for Frequency Set Point 2 of the memory interface 0/1. Only valid for LPDDR5 protocol.

[Fields]

[31:0] FREQ_KHZ_FSP2: Memory clock frequency in KHz for Frequency Set Point 2.
MEMCLK_FREQ_FSP2_INTF1 0x2AC
MEM_WIDTH_INFO_INTF0 0x230

[Output] Memory Width Information

This register provides the memory width information for the memory interface 0/1.

[Fields]

[23:16] C_WIDTH: Channel width.

[15:8] CS_WIDTH: Chip select width.

[7:0] DQ_WIDTH: Data width
MEM_WIDTH_INFO_INTF1 0x2B0
MEM_TOTAL_CAPACITY_INTF0 0x234

Output] Total Memory Capacity

This register reports the total memory capacity per channel in gigabits (Gb) for the memory interface 0/1.

[Fields]

[7:0] CAPACITY_GBITS: Total memory device capacity per channel in Gb. Total memory capacity is calculated as:

CAPACITY = (DQ_WIDTH / DEVICE_WIDTH) * NUM_RANKS * C_WIDTH * DEVICE_DENSITY
MEM_TOTAL_CAPACITY_INTF1 0x2B4
ECC_ENABLE_INTF0 0x240

[Output] ECC Enable Status

This register provides detailed information regarding the ECC enable status and type for the memory interface 0/1.

[Fields]

[18:18] RD_LINK_ECC_ENABLED: Indicates the Read Link-ECC enable status.

  • 1'b1 – Read Link-ECC is enabled.
  • 1'b0 – Read Link-ECC is disabled.

[17:17] WR_LINK_ECC_ENABLED: Indicates the Write Link-ECC enable status.

  • 1'b1 – Write Link-ECC is enabled.
  • 1'b0 – Write Link-ECC is disabled.

[16:16] LINK_ECC_SUPPORTED: Indicates if Link-ECC is supported by the interface.

  • 1'b1 – Link-ECC is supported.
  • 1'b0 – Link-ECC is not supported.

[8:8] ECC_TYPE: Specifies the ECC operational mode.

  • 1'b0 – Out-of-Band ECC.
  • 1'b1 – In-line ECC.
[1:0] ECC_ENABLE_TYPE: Reports the current ECC error reporting and correcting status.
  • 1'b00 – ECC is disabled. Data will be written and returned without ECC verification.
  • 1'b01 – ECC is enabled without error detection or correction.
  • 1'b10 – ECC is enabled with error detection; errors are reported but not corrected.
  • 1'b11 – ECC is enabled with error detection and correction; single-bit errors are automatically corrected.
ECC_ENABLE_INTF1 0x2C0
ECC_SCRUB_STATUS_INTF0 0x244

[Output] ECC Scrub Status

This register indicates the ECC scrub operation status for the memory interface 0/1.

[Fields]

[1:1] ECC_SCRUB_IN_PROGRESS: Reports whether an ECC scrub operation is currently in progress.
  • 1'b0 – Not actively performing a scrubbing operation.
  • 1'b1 – The Controller is in the process of performing a scrubbing operation.
[0:0] ECC_SCRUB_STATUS: The ECC scrub operation initiated using ECC_SCRUB_MODE_0/1_START mailbox command has completed.
  • 1'b0 – Scrubbing operation has not completed.
  • 1'b1 – Scrubbing operation has completed.
ECC_SCRUB_STATUS_INTF1 0x2C4
LP_MODE_INTF0 0x250

[Output] Low Power Mode Status

This register provides the current low power state and its validity for the memory interface 0/1.

[Fields]

[5:0] LP_STATE: Current Interface Low Power State.
  • 1'b000000 – Idle.
  • 1'b000001 – Active Power Down.
  • 1'b000010 – Active Power Down with Memory Clock Gating.
  • 1'b000011 – Pre-Charge Power Down.
  • 1'b000100 – Pre-Charge Power Down with Memory Clock Gating.
  • 1'b000101 – Self-Refresh Short.
  • 1'b000110 – Self-Refresh Short with Memory Clock Gating.
  • 1'b001000 – Self-Refresh Long.
  • 1'b001001 – Self-Refresh Long with Memory Clock Gating.
  • 1'b001010 – Self-Refresh Long with Memory Clock and Controller Clock Gating.
  • 1'b001011 – Self-Refresh Power Down Short.
  • 1'b001100 – Self-Refresh Power Down Short with Memory Clock Gating.
  • 1'b001101 – Self-Refresh Power Down.
  • 1'b001110 – Self-Refresh Power Down Long with Memory Clock Gating.
  • 1'b001111 – Self-Refresh Power Down Long with Memory and Controller Clock Gating.
[6:6] LP_STATE_VALID: Indicates whether the data for the low power state is valid.
  • 1'b1 – Valid. The low power state information is reliable.
  • 1'b0 – Invalid. The interface is currently transitioning into or out of a low power state.
LP_MODE_INTF1 0x2D0
MEM_INIT_STATUS_INTF0 0x260

[Output] BIST Memory Initialization Status

This register holds the status of the BIST memory initialization operation for the memory interface specified by the instance ID. The value of this register is only valid if the mailbox command BIST_MEM_INIT_START was issued previously.

[Fields]

[0:0] MEM_INIT_STATUS: Indicates the status of the BIST memory content initialization operation.
  • 1'b0 – Memory content initialization operation still in progress if previously initiated.
  • 1'b1 – Memory content initialization operation has been completed.
MEM_INIT_STATUS_INTF1 0x2E0
BIST_STATUS_INTF0 0x264

[Output] BIST Results Status

This register contains BIST results for the previously initiated BIST operation for memory interface 0/1

[Fields]

[31:16] BIST_FAIL_RESULT_OFFSET: Holds the offset pointer of the BIST failure results. The data at the pointer location will be as below:
  • OFFSET [0] to OFFSET [8]: [287:0] BIST_EXP_DATA - Holds the expected read data for BIST data check failure.
  • OFFSET [9] to OFFSET [10]: [37:0] BIST_FAIL_ADDR - Holds the actual failing address for BIST data check failure.
  • OFFSET [11] to OFFSET [20]: [287:0] BIST_FAIL_DATA - Holds the actual failing data for BIST data check failure. [15:8] BIST_FAIL_RESULT_SIZE: Holds the size of the BIST failure results. The value of this will be 640 bits.
[1:1] BIST_RESULT: Holds the result of the BIST operation. For this BIST mode, the test will end at the first failure, or completely check the specified data range if no failures were found. This value is valid when BIST_STATUS indicates that the BIST operation has completed.
  • 1'b0 = Data check failed.
  • 1'b1 = Data check passed.
[0:0] BIST_STATUS: Indicates the status of the BIST operation.
  • 1'b0 – BIST operation still in progress if previously initiated.
  • 1'b1 – BIST operation has been completed.
BIST_STATUS_INTF1 0x2E4
ECC_ERR_STATUS 0x300

[Output] ECC Error Status

This register contains the status of the ECC error buffer.

[Fields]

[31:16] ECC_ERR_OVERFLOW: This field indicates that buffer overflow has occurred due to a new ECC interrupt occurring after the ECC error buffer is at full capacity of 16 entries. Each new interrupt type that cannot be enqueued into the buffer are logically-OR’d to the existing contents of the overflow status field. The ECC interrupt types indicated by the different positional bits in the overflow field are as below:
  • [0] – Single-bit error.
  • [1] – Multiple single-bit errors.
  • [2] – Double-bit error.
  • [3] – Multiple double-bit errors.
  • [8] – Single-bit error during ECC scrubbing.
  • [9] – Write link ECC single-bit error (LPDDR5 only).
  • [10] – Write link ECC double-bit error (LPDDR5 only).
  • [11] – Read link ECC single-bit error (LPDDR5 only).
  • [12] – Read link ECC double-bit error (LPDDR5 only).
  • [13] – RMW read link ECC double-bit error (LPDDR5 only).

[15:0] ECC_ERR_COUNTER: This field indicates the number of entries in ECC error buffer. The buffer has a maximum capacity of 16 entries after which overflow occurs. The mailbox command ECC_CLEAR_ERR_BUFFER clears the ECC error buffer and resets the ECC_ERR_COUNTER to 0.

ECC_ERR_DATA_START 0x310

[Output] ECC Error Data Start

This register is the start of the ECC error data buffer. The buffer has a maximum capacity of 16 ECC errors. Each ECC error data entry has a size of 64 bits arranged in two 32-bit registers (Register 1 and Register 2 ). The mailbox command ECC_CLEAR_ERR_BUFFER clears the ECC error buffer and resets the ECC_ERR_COUNTER to 0.

[Fields]

R1[24:22] IP_TYPE: This field specifies the IP type of the interface that produced the ECC interrupt. IP_TYPE of 0 indicates that the buffer entry is not populated with valid data.

R1[21:17] INSTANCE_ID: This field specifies the instance ID of the interface that produced the ECC interrupt.

R1[16:10] ECC_ERR_SOURCE_ID: This field specifies the source ID associated with the ECC event. For AXI ports, the source ID is comprised of the Port ID (upper bit/s) and the Requestor ID, where the Requestor ID is the axi0_AWID for write commands or the axi0_ARID for read commands.

R1[9:6] ECC_ERR_TYPE: This field specifies the ECC interrupt type of the ECC event.
  • 1'b0000 – Single-bit error.
  • 1'b0001 – Multiple single-bit errors.
  • 1'b0010 – Double-bit error.
  • 1'b0011 – Multiple double-bit errors.
  • 1'b1000 – Single-bit error during ECC scrubbing.
  • 1'b1001 – Write link ECC single-bit error (LPDDR5 only).
  • 1'b1010 – Write link ECC double-bit error (LPDDR5 only).
  • 1'b1011 – Read link ECC single-bit error (LPDDR5 only)
  • 1'b1100 – Read link ECC double-bit error (LPDDR5 only).
  • 1'b1101 – Read link ECC double-bit error, caused by read-modify-write operation (LPDDR5 only).

R1[5:0] ECC_ERR_ADDR_UPPER: This field specifies the upper 6 bits of the address of the read data that caused the ECC event. The Controller will pad this parameter with zeros for any address bits not used by the controller.

R2[31:0] ECC_ERR_ADDR_LOWER: This field specifies the lower 32 bits of the address of the read data that caused the ECC event. The Controller will pad this parameter with zeros for any address bits not used by the controller.

Note: Refer to ECC Error Handling for information on ECC Error Buffer Byte Offset.
STATUS 0x400

[Output] Status Register

“At a Glance” status register. This field is automatically updated by the Calibration IOSSM and no explicit operation is required to trigger an update.

  • 1'b001 – Calibration was successful.
  • 1'b010 – Calibration failed.
  • 1'b100 – Calibration ongoing.
  • 1'b000 – Interface unused.
STATUS_CAL_INTF0 0x404

[Output] Memory Calibration Status

This register provides the calibration status for memory interface 0/1.

[Fields]

[2:0] STATUS: Calibration Status of memory interface
  • 1'b001 – Calibration was successful.
  • 1'b010 – Calibration failed.
  • 1'b100 – Calibration ongoing.
  • 1'b000 – Interface unused.
STATUS_CAL_INTF1 0x408

Mailbox Supported Commands

The following registers require handshaking procedures with the mailbox for successful retrieval of information. Refer to the instructions described in Sending a Mailbox Command for more information on handshaking procedures.

Table 241.  Supported Commands
CMD_TYPE Enum CMD_OPCODE Enum Value
CMD_TRIG_CONTROLLER_OP (value=0x4) ECC_ENABLE_SET 0x0101
ECC_INTERRUPT_MASK 0x0105
ECC_WRITEBACK_ENABLE 0x0106
ECC_INJECT_ERROR 0x0109
ECC_CLEAR_ERR_BUFFER 0x0110
ECC_SCRUB_MODE_0_START 0x0202
ECC_SCRUB_MODE_1_START 0x0203
BIST_STANDARD_MODE_START 0x0301
BIST_MEM_INIT_START 0x0303
BIST_SET_DATA_PATTERN_UPPER 0x0305
BIST_SET_DATA_PATTERN_LOWER 0x0306
CHANGE_FSP_LP5 0x0c01
LP_MODE_ENTER 0x0d01
LP_MODE_EXIT 0x0d02
LP_MODE_AUTO 0x0d04

CMD_TRIG_MEM_CAL_OP ​ (value=0x5)

 TRIG_MEM_CAL 0x000a
Level Two Title