External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

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ID 772538
Date 3/31/2025
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Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP 2. Agilex™ 7 M-Series FPGA EMIF IP – Introduction 3. Agilex™ 7 M-Series FPGA EMIF IP – Product Architecture 4. Agilex™ 7 M-Series FPGA EMIF IP – End-User Signals 5. Agilex™ 7 M-Series FPGA EMIF IP – Simulating Memory IP 6. Agilex™ 7 M-Series FPGA EMIF IP – DDR4 Support 7. Agilex™ 7 M-Series FPGA EMIF IP – DDR5 Support 8. Agilex™ 7 M-Series FPGA EMIF IP – LPDDR5 Support 9. Agilex™ 7 M-Series FPGA EMIF IP – Timing Closure 10. Agilex™ 7 M-Series FPGA EMIF IP – Controller Optimization 11. Agilex™ 7 M-Series FPGA EMIF IP – Debugging 12. Agilex™ 7 FPGA EMIF IP - Mailbox Support 13. Document Revision History for External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP x
1.1. Release Information
2. Agilex™ 7 M-Series FPGA EMIF IP – Introduction x
2.1. Agilex™ 7 M-Series EMIF IP Protocol and Feature Support 2.2. Agilex™ 7 M-Series EMIF IP Design Flow 2.3. Agilex™ 7 M-Series EMIF IP Design Checklist
3. Agilex™ 7 M-Series FPGA EMIF IP – Product Architecture x
3.1. Agilex™ 7 M-Series EMIF Architecture: Introduction 3.2. Agilex™ 7 M-Series EMIF Sequencer 3.3. Agilex™ 7 M-Series EMIF Controller 3.4. Agilex™ 7 M-Series EMIF IP Interface Protocol: Interface Width, User Access Mode, and ECC 3.5. Agilex™ 7 M-Series EMIF IP for Hard Processor Subsystem (HPS)
3.1. Agilex™ 7 M-Series EMIF Architecture: Introduction x
3.1.1. Agilex™ 7 M-Series EMIF Architecture: I/O Subsystem 3.1.2. Agilex™ 7 M-Series EMIF Architecture: I/O SSM 3.1.3. Agilex™ 7 M-Series EMIF Architecture: I/O Bank 3.1.4. Agilex™ 7 M-Series EMIF Architecture: I/O Lane 3.1.5. Agilex™ 7 M-Series EMIF Architecture: Input DQS Clock Tree 3.1.6. Agilex™ 7 M-Series EMIF Architecture: PHY Clock Tree 3.1.7. Agilex™ 7 M-Series EMIF Architecture: PLL Reference Clock Networks 3.1.8. Agilex™ 7 M-Series EMIF Architecture: Clock Phase Alignment 3.1.9. User Clock in Different Core Access Modes
3.1.3. Agilex™ 7 M-Series EMIF Architecture: I/O Bank x
3.1.3.1. I/O Byte Lane Organization in Different Agilex™ 7 M-Series Devices 3.1.3.2. Lockstep Configuration 3.1.3.3. DDR4 Pin Placement 3.1.3.4. DDR5 Pin Placement 3.1.3.5. LPDDR5 Pin Placement 3.1.3.6. I/O Sub-Bank Usage
3.3. Agilex™ 7 M-Series EMIF Controller x
3.3.1. Hard Memory Controller
3.3.1. Hard Memory Controller x
3.3.1.1. Hard Memory Controller Features
3.5. Agilex™ 7 M-Series EMIF IP for Hard Processor Subsystem (HPS) x
3.5.1. Restrictions on I/O Bank Usage for Agilex™ 7 M-Series EMIF IP with HPS
3.5.1. Restrictions on I/O Bank Usage for Agilex™ 7 M-Series EMIF IP with HPS x
3.5.1.1. Using the Legacy EMIF Debug Toolkit with Agilex™ 7 M-Series HPS Interfaces
4. Agilex™ 7 M-Series FPGA EMIF IP – End-User Signals x
4.1. IP Interfaces for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.2. IP Interfaces for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.3. IP Interfaces for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.4. IP Interfaces for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.5. IP Interfaces for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5
4.1. IP Interfaces for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component x
4.1.1. s0_axi4_clock_in for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.2. s0_axi4_clock_out for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.3. s0_axi4_ctrl_ready for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.4. core_init_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.5. s0_axi4 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.6. s0_axi4lite_clock for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.7. s0_axi4lite_reset_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.8. s0_axi4lite for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.9. mem_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.10. mem_ck_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.11. mem_reset_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.12. oct_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.13. ref_clk for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component
4.2. IP Interfaces for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM x
4.2.1. s0_axi4_clock_in for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.2. s0_axi4_clock_out for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.3. s0_axi4_ctrl_ready for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.4. core_init_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.5. s0_axi4 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.6. s0_axi4lite_clock for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.7. s0_axi4lite_reset_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.8. s0_axi4lite for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.9. mem_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.10. mem_ck_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.11. mem_reset_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.12. oct_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.13. ref_clk for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM
4.3. IP Interfaces for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component x
4.3.1. s0_axi4_clock_in for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.2. s0_axi4_clock_out for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.3. s0_axi4_ctrl_ready for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.4. core_init_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.5. s0_axi4 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.6. s1_axi4 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.7. s0_axi4lite_clock for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.8. s0_axi4lite_reset_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.9. s0_axi4lite for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.10. mem_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.11. mem_ck_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.12. mem_reset_n_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.13. mem_1 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.14. mem_ck_1 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.15. mem_reset_n_1 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.16. oct_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.17. oct_1 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.18. ref_clk for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component
4.4. IP Interfaces for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM x
4.4.1. s0_axi4_clock_out for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.2. s0_axi4_ctrl_ready for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.3. s1_axi4_clock_out for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.4. s1_axi4_ctrl_ready for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.5. s0_axi4_clock_in for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.6. core_init_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.7. s0_axi4 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.8. s1_axi4 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.9. s0_axi4lite_clock for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.10. s0_axi4lite_reset_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.11. s0_axi4lite for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.12. s1_axi4lite_clock for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.13. s1_axi4lite_reset_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.14. s1_axi4lite for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.15. mem_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.16. mem_1 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.17. mem_reset_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.18. mem_ck_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.19. mem_ck_1 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.20. mem_i3c for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.21. mem_lb_dq for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.22. mem_lb_dqs for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.23. oct_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.24. oct_1 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.25. ref_clk for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM
4.5. IP Interfaces for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 x
4.5.1. s0_axi4_clock_in for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.2. core_init_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.3. s0_axi4_ctrl_ready for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.4. s0_axi4_clock_out for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.5. s1_axi4_ctrl_ready for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.6. s1_axi4_clock_out for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.7. s0_axi4 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.8. s1_axi4 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.9. s2_axi4 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.10. s3_axi4 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.11. s0_axi4lite_clock for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.12. s0_axi4lite_reset_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.13. s0_axi4lite for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.14. s1_axi4lite_clock for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.15. s1_axi4lite_reset_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.16. s1_axi4lite for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.17. mem_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.18. mem_ck_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.19. mem_1 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.20. mem_ck_1 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.21. mem_2 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.22. mem_ck_2 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.23. mem_3 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.24. mem_ck_3 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.25. mem_reset_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.26. oct_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.27. oct_1 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.28. oct_2 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.29. oct_3 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.30. ref_clk for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5
5. Agilex™ 7 M-Series FPGA EMIF IP – Simulating Memory IP x
5.1. Simulation Walkthrough
5.1. Simulation Walkthrough x
5.1.1. Calibration 5.1.2. Simulation Scripts 5.1.3. Functional Simulation with Verilog HDL 5.1.4. Simulating the Design Example
6. Agilex™ 7 M-Series FPGA EMIF IP – DDR4 Support x
6.1. External Memory Interfaces (EMIF) IP - DDR4 Component Parameter Descriptions 6.2. External Memory Interfaces (EMIF) IP - DDR4 DIMM Parameter Descriptions 6.3. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning 6.4. DDR4 Board Design Guidelines
6.3. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning x
6.3.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins 6.3.2. Agilex™ 7 M-Series FPGA EMIF IP Resources 6.3.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP 6.3.4. Pin Placements for Agilex™ 7 M-Series FPGA DDR4 EMIF IP
6.3.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins x
6.3.1.1. Estimating Pin Requirements 6.3.1.2. DIMM Options 6.3.1.3. Maximum Number of Interfaces
6.3.2. Agilex™ 7 M-Series FPGA EMIF IP Resources x
6.3.2.1. OCT 6.3.2.2. PLL
6.3.4. Pin Placements for Agilex™ 7 M-Series FPGA DDR4 EMIF IP x
6.3.4.1. Address and Command Pin Placement for DDR4 6.3.4.2. DDR4 Data Width Mapping 6.3.4.3. General Guidelines - DDR4 6.3.4.4. x4 DIMM Implementation 6.3.4.5. Specific Pin Connection Requirements 6.3.4.6. Command and Address Signals 6.3.4.7. Clock Signals 6.3.4.8. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.4. DDR4 Board Design Guidelines x
6.4.1. Terminations for DDR4 with Agilex™ 7 M-Series Devices 6.4.2. General Layout Routing Guidelines 6.4.3. Reference Stackup 6.4.4. Agilex™ 7 M-Series EMIF-Specific Routing Guidelines for Various DDR4 Topologies 6.4.5. DDR4 Routing Guidelines: Discrete (Component) Topologies
6.4.1. Terminations for DDR4 with Agilex™ 7 M-Series Devices x
6.4.1.1. Dynamic On-Chip Termination (OCT) 6.4.1.2. Dynamic On-Die Termination (ODT) in DDR4 6.4.1.3. Choosing Terminations on Agilex™ 7 M-Series FPGA Devices 6.4.1.4. On-Chip Termination Recommendations for Agilex™ 7 M-Series FPGA Devices
6.4.4. Agilex™ 7 M-Series EMIF-Specific Routing Guidelines for Various DDR4 Topologies x
6.4.4.1. One DIMM per Channel (1DPC) for UDIMM, RDIMM, and SODIMM DDR4 Topologies 6.4.4.2. Skew Matching Guidelines for DIMM Configurations 6.4.4.3. Power Delivery Recommendations for the Memory / DIMM Side
6.4.5. DDR4 Routing Guidelines: Discrete (Component) Topologies x
6.4.5.1. Single Rank and Dual Rank x 8 Discrete (Component) Topology 6.4.5.2. Single Rank x16 and Dual Rank x16 Discrete (Component) Topology 6.4.5.3. ADDR/CMD Reference Voltage/RESET Signal Routing Guidelines for Single Rank x 8 and Single Rank x 16 Discrete (Component) Topologies 6.4.5.4. Skew Matching Guidelines for DDR4 Discrete Configurations 6.4.5.5. Power Delivery Recommendations for DDR4 Discrete Configurations 6.4.5.6. Agilex™ 7 M-Series EMIF Pin Swapping Guidelines
6.4.5.6. Agilex™ 7 M-Series EMIF Pin Swapping Guidelines x
6.4.5.6.1. DDR4 Byte Lane Swapping 6.4.5.6.2. DDR4 Address and Command and CLK Lane 6.4.5.6.3. DDR4 Interface x8 Data Lane 6.4.5.6.4. DDR4 Interface x4 Data Lane 6.4.5.6.5. Pin Swizzling
7. Agilex™ 7 M-Series FPGA EMIF IP – DDR5 Support x
7.1. External Memory Interfaces (EMIF) IP - DDR5 Component Parameter Descriptions 7.2. External Memory Interfaces (EMIF) IP - DDR5 DIMM Parameter Descriptions 7.3. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning 7.4. DDR5 Board Design Guidelines
7.3. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning x
7.3.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins 7.3.2. Agilex™ 7 M-Series FPGA EMIF IP Resources 7.3.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP 7.3.4. Pin Placements for Agilex™ 7 M-Series FPGA DDR5 EMIF IP 7.3.5. Agilex™ 7 M-Series EMIF Pin Swapping Guidelines
7.3.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins x
7.3.1.1. Estimating Pin Requirements 7.3.1.2. DIMM Options 7.3.1.3. Maximum Number of Interfaces
7.3.2. Agilex™ 7 M-Series FPGA EMIF IP Resources x
7.3.2.1. OCT 7.3.2.2. PLL
7.3.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP x
7.3.3.1. General Guidelines - DDR5 7.3.3.2. x4 DIMM Implementation 7.3.3.3. Specific Pin Connection Requirements 7.3.3.4. Command and Address Signals 7.3.3.5. Clock Signals 7.3.3.6. Data, Data Strobes, DM, and Optional ECC Signals
7.3.4. Pin Placements for Agilex™ 7 M-Series FPGA DDR5 EMIF IP x
7.3.4.1. Address and Command Pin Placement for DDR5 7.3.4.2. DDR5 Data Width Mapping
7.3.5. Agilex™ 7 M-Series EMIF Pin Swapping Guidelines x
7.3.5.1. DDR5 Byte Lane Swapping 7.3.5.2. DDR5 Address and Command and CLK Lane 7.3.5.3. DDR5 Interface x8 Data Lane 7.3.5.4. DDR5 Interface x4 Data Lane 7.3.5.5. Pin Swizzling
7.4. DDR5 Board Design Guidelines x
7.4.1. PCB Stack-up and Design Considerations 7.4.2. General Design Considerations 7.4.3. DDR Differential Signals Routing 7.4.4. Ground Plane and Return Path 7.4.5. RDIMM, UDIMM, and SODIMM Break-in Layout Guidelines 7.4.6. DRAM Break-in Layout Guidelines 7.4.7. General Notes for EMIF Routing Guidelines Tables 7.4.8. DDR5 PCB Layout Guidelines 7.4.9. DDR5 RDIMM Power Management IC 7.4.10. DDR5 Simulation Strategy
7.4.8. DDR5 PCB Layout Guidelines x
7.4.8.1. DDR5 Discrete Component/Memory Down Topology: Single Rank x8 or x16, Dual Rank x8 or x16 7.4.8.2. Routing Guidelines for DDR5 Memory Down: Single Rank or Dual Rank (x8 bit or x16 bit) Configurations 7.4.8.3. Routing Guidelines for DDR5 RDIMM, UDIMM, and SODIMM Configurations 7.4.8.4. Example of a DDR5 layout on an Altera FPGA Platform Board
8. Agilex™ 7 M-Series FPGA EMIF IP – LPDDR5 Support x
8.1. External Memory Interfaces (EMIF) IP - LPDDR5 Parameter Descriptions 8.2. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning 8.3. LPDDR5 Board Design Guidelines
8.2. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning x
8.2.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins 8.2.2. Agilex™ 7 M-Series FPGA EMIF IP Resources 8.2.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP 8.2.4. Pin Placements for Agilex™ 7 M-Series FPGA LPDDR5 EMIF IP
8.2.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins x
8.2.1.1. Estimating Pin Requirements 8.2.1.2. LPDDR5 Component Options 8.2.1.3. Maximum Number of Interfaces
8.2.2. Agilex™ 7 M-Series FPGA EMIF IP Resources x
8.2.2.1. OCT 8.2.2.2. PLL
8.2.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP x
8.2.3.1. General Guidelines - LPDDR5 8.2.3.2. Specific Pin Connection Requirements 8.2.3.3. Command and Address Signals 8.2.3.4. Clock Signals
8.2.4. Pin Placements for Agilex™ 7 M-Series FPGA LPDDR5 EMIF IP x
8.2.4.1. Address and Command Pin Placement for LPDDR5 8.2.4.2. LPDDR5 Data Width Mapping 8.2.4.3. LPDDR5 Byte Lane Swapping
8.3. LPDDR5 Board Design Guidelines x
8.3.1. PCB Stack-up and Design Considerations 8.3.2. General Design Considerations 8.3.3. DDR Differential Signals Routing 8.3.4. Ground Plane and Return Path 8.3.5. DRAM Break-in Layout Guidelines 8.3.6. General Notes for EMIF Routing Guidelines Tables 8.3.7. LPDDR5 PCB Layout Guidelines 8.3.8. LPDDR5 Simulation Strategy
8.3.7. LPDDR5 PCB Layout Guidelines x
8.3.7.1. LPDDR5 Discrete Component/Memory Down Topology, Single Rank or Dual Rank 8.3.7.2. Routing Guidelines for LPDDR5 Memory Down Topology 8.3.7.3. Example of an LPDDR5 Layout on an Altera® FPGA Platform Board
9. Agilex™ 7 M-Series FPGA EMIF IP – Timing Closure x
9.1. Timing Closure 9.2. Optimizing Timing
9.1. Timing Closure x
9.1.1. Timing Analysis
9.1.1. Timing Analysis x
9.1.1.1. PHY or Core
10. Agilex™ 7 M-Series FPGA EMIF IP – Controller Optimization x
10.1. mrh_Optimizing Efficiency for Secondary Controller 10.2. Interface Standard 10.3. Bank Management Efficiency 10.4. Data Transfer 10.5. Improving Controller Efficiency
10.5. Improving Controller Efficiency x
10.5.1. Using Multiple AXI IDs 10.5.2. Frequency of Operation 10.5.3. Series of Reads or Writes 10.5.4. AXI to Memory Mapping
11. Agilex™ 7 M-Series FPGA EMIF IP – Debugging x
11.1. Interface Configuration Performance Issues 11.2. Functional Issue Evaluation 11.3. Timing Issue Characteristics 11.4. Verifying Memory IP Using the Signal Tap Logic Analyzer 11.5. Debugging with the External Memory Interface Debug Toolkit 11.6. Generating Traffic with the Test Engine IP 11.7. Guidelines for Developing HDL for Traffic Generator 11.8. Guidelines for Traffic Generator Status Check 11.9. Hardware Debugging Guidelines 11.10. Categorizing Hardware Issues 11.11. Debugging Intermittent Issues
11.1. Interface Configuration Performance Issues x
11.1.1. Interface Configuration Bottleneck and Efficiency Issues
11.2. Functional Issue Evaluation x
11.2.1. Altera IP Memory Model 11.2.2. Vendor Memory Model 11.2.3. Transcript Window Messages
11.3. Timing Issue Characteristics x
11.3.1. Evaluating FPGA Timing Issues 11.3.2. Evaluating External Memory Interface Timing Issues
11.5. Debugging with the External Memory Interface Debug Toolkit x
11.5.1. Prerequisites for Using the EMIF Debug Toolkit 11.5.2. Configuring Your Design to Use the EMIF Debug Toolkit 11.5.3. Launching the EMIF Debug Toolkit 11.5.4. Using the EMIF Debug Toolkit
11.5.4. Using the EMIF Debug Toolkit x
11.5.4.1. Rerunning Calibration 11.5.4.2. Rerunning the Test Engine 11.5.4.3. Saving Debug Print 11.5.4.4. Calibration Reports 11.5.4.5. Driver Margining Tab 11.5.4.6. Pin Delay Settings Tab
11.8. Guidelines for Traffic Generator Status Check x
11.8.1. Status Check Using the Signal Tap Logic Analyzer 11.8.2. Exporting the Status Interface to the Top-Level Design
11.9. Hardware Debugging Guidelines x
11.9.1. Create a Simplified Design that Demonstrates the Same Issue 11.9.2. Measure Power Distribution Network 11.9.3. Measure Signal Integrity and Setup and Hold Margin 11.9.4. Vary Voltage 11.9.5. Operate at a Lower Speed 11.9.6. Determine Whether the Issue Exists in Previous Versions of Software 11.9.7. Determine Whether the Issue Exists in the Current Version of Software 11.9.8. Try A Different PCB 11.9.9. Try Other Configurations 11.9.10. Debugging Checklist
11.10. Categorizing Hardware Issues x
11.10.1. Signal Integrity Issues 11.10.2. Hardware and Calibration Issues
11.10.1. Signal Integrity Issues x
11.10.1.1. Characteristics of Signal Integrity Issues 11.10.1.2. Evaluating Signal Integrity Issues
11.10.1.2. Evaluating Signal Integrity Issues x
11.10.1.2.1. Skew 11.10.1.2.2. Crosstalk 11.10.1.2.3. Power System 11.10.1.2.4. Clock Signals 11.10.1.2.5. Address and Command Signals 11.10.1.2.6. Read Data Valid Window and Eye Diagram 11.10.1.2.7. Write Data Valid Window and Eye Diagram
11.10.2. Hardware and Calibration Issues x
11.10.2.1. Verifying High-Level Configuration Memory Device Pin Swizzle map Pin Swizzle Map for Component Interfaces Pin Swizzle Map for DIMM interface 11.10.2.2. Verifying Memory Timing Parameters 11.10.2.3. Verifying the Correct Memory Component or DIMM is Installed
12. Agilex™ 7 FPGA EMIF IP - Mailbox Support x
12.1. Agilex™ 7 Mailbox Structure and Register Definitions
12.1. Agilex™ 7 Mailbox Structure and Register Definitions x
12.1.1. Mailbox Supported Commands 12.1.2. Mailbox Command Definitions 12.1.3. ECC Syndrome Codes 12.1.4. ECC Error Handling 12.1.5. Accessing Read-Only Registers 12.1.6. Sending a Mailbox Command 12.1.7. IOSSM Mailbox Access Script
12.1.5. Accessing Read-Only Registers x
12.1.5.1. Example 1: Reading IP_TYPE and IP_INSTANCE_ID of All the Interfaces in the IO96B Through Read-Only Registers 12.1.5.2. Example 2: Reading the Memory Clock Frequency for an Interface
12.1.6. Sending a Mailbox Command x
12.1.6.1. Example 3: Sending Recalibration Request and Reading Calibration Status Using the Mailbox
12.1.6.1. Example 3: Sending Recalibration Request and Reading Calibration Status Using the Mailbox x
12.1.6.1.1. Example 4: Sending ECC_INJECT_ERROR Using the Mailbox and Reading ECC Error Status, ECC Error Buffer Registers
12.1.7. IOSSM Mailbox Access Script x
12.1.7.1. Mailbox Script Overview 12.1.7.2. Running the Mailbox Script
12.1.7.1. Mailbox Script Overview x
12.1.7.1.1. mb_iossm_command.tcl 12.1.7.1.2. mb_user_input.tcl
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP
2. Agilex™ 7 M-Series FPGA EMIF IP – Introduction
3. Agilex™ 7 M-Series FPGA EMIF IP – Product Architecture
4. Agilex™ 7 M-Series FPGA EMIF IP – End-User Signals
5. Agilex™ 7 M-Series FPGA EMIF IP – Simulating Memory IP
6. Agilex™ 7 M-Series FPGA EMIF IP – DDR4 Support
7. Agilex™ 7 M-Series FPGA EMIF IP – DDR5 Support
8. Agilex™ 7 M-Series FPGA EMIF IP – LPDDR5 Support
9. Agilex™ 7 M-Series FPGA EMIF IP – Timing Closure
10. Agilex™ 7 M-Series FPGA EMIF IP – Controller Optimization
11. Agilex™ 7 M-Series FPGA EMIF IP – Debugging
12. Agilex™ 7 FPGA EMIF IP - Mailbox Support
13. Document Revision History for External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

11.10.2.1. Verifying High-Level Configuration

Memory Device

Verify that you select the correct memory Number of Channels, Data DQ Width, Die Density, and CS Width for the memory configuration used. Inaccurate information can result in calibration failure or traffic failure.

The example below shows memory parameterization based on the Agilex™ 7 FPGA M-Series Development Kit targeting an MT62F512M32D2 LPDDR5 EMIF configuration.

Figure 87. MT62F512M32D2 LPDDR5 EMIF Configuration
  • Number of Channels: 2 (Dedicated A/C pins for each channel.)
  • Data DQ Width: 16 (DQ pins per memory channel.)
  • Die Density: 8 Gbits (Select capacity of each memory die <in Gbits>, not total memory density per package.)
  • CS width: 1 (Above topology is single-rank per channel. MT62F512M32D2 supports single-rank per die per channel based on the die organization in memory component datasheet.)
Figure 88. Example EMIF IP High Level Configuration for Configuration shown Above

Another example showing a configuration based on Agilex™ 7 FPGA M-Series Development Kit targeting DDR5 RDIMM is shown below.

Figure 89. DDR5 RDIMM Slot Using MTC10F1084S1RC56BG1 Module
Figure 90. MTC10F1084S1RC56BG1 DDR5 RDIMM
  • DIMM Type: RDIMM.
  • Data DQ Width: 32 (DQ pins per memory channel, used for data.)
  • ECC DQ Width: 8 (Additional DQ pins per channel, used for ECC.)
  • Die DQ Width: 8 (Numbers of DQ pins in each die. For dual-die package, select width of each die, not width of full package.)
  • Die Density: 16Gbits (Select capacity of each memory die <in Gbits> per channel per die. For dual-die package, this is the density of each die, not the density of the full package.)
  • CS width: 1 (Above topology is Single Rank per channel.)
Figure 91. Example EMIF IP High Level Configuration for configuration shown Above

Pin Swizzle map

The Quartus® Prime software uses fixed pin placement for each supported memory standard, as described in the Product Architecture chapter. Do not change pin placement using a .qsf assignment or the pin planner if you need to swap the DQ pins within a DQS group or swap the DQS group within a channel or interface. You may encounter fitter errors if you enter incorrect pin locations for the EMIF interface. The example below shows fitter error for LPDDR5 protocol when an incorrect pin location is used. 

Error (175001): The Fitter cannot place 1 BYTE, which is within Generic Component ed_synth_emif_io96b_lpddr5_0.

The Pin Swizzle Map allows you to inform the EMIF IP about the ordering of the physical connections of each DQ pin on the memory component to the FPGA. Incorrect information entered in the pin swizzle map may cause calibration errors.

Refer to the External Memory Interfaces Agilex™ 7 M-Series FPGA IP Design Example User Guide for details on configuring DQ pin swizzling.

Figure 92. Example of Pin Swizzle Map Entry

Pin Swizzle Map for Component Interfaces

For component type interfaces, you must match the net name in the schematic to the index of default pin placements, to determine the pin swizzling specification.

Consider the example in the table below, which represents DQS group 1 for channel 1 on the LPDDR5 component interface on the Agilex™ 7 FPGA M-Series Development Kit with MT62F512M32D2 memory.

Table 235.  Example of Pin Swizzle Targeting Component Type Memory Interface
Lane Pin Pin Index Default Pin Placement Net Name in Schematic Swizzling index
BL6 K57 83 MEM_1_MEM_DQ [7] MEM_1_MEM_DQ [14] 14
L56 82 MEM_1_MEM_DQ [6] MEM_1_MEM_DQ [12] 12
H57 81 MEM_1_MEM_DQ [5] MEM_1_MEM_DQ [13] 13
G56 80 MEM_1_MEM_DQ [4] MEM_1_MEM_DQ [11] 11
K55 79      
L54 78 MEM_1_MEM_DM_N [0] MEM_1_MEM_DM_N [1]  
H55 77 MEM_1_MEM_RDQS_C [0] MEM_1_MEM_RDQS_C [1]  
G54 76 MEM_1_MEM_RDQS_T [0] MEM_1_MEM_RDQS_T [1]  
K53 75 MEM_1_MEM_DQ [3] MEM_1_MEM_DQ [9] 9
L52 74 MEM_1_MEM_DQ [2] MEM_1_MEM_DQ [10] 10
H53 73 MEM_1_MEM_DQ [1] MEM_1_MEM_DQ [8] 8
G52 72 MEM_1_MEM_DQ [0] MEM_1_MEM_DQ [15] 15

For this specific group, the correct pin swizzling specification is:

PIN_SWIZZLE_CH1_DQS1 = 15,8,10,9,11,13,12,14;

The sample below shows pin swizzle map parameters based on Agilex™ 7 M-Series Development Kit targeting LPDDR5 EMIF. All parameters must be added in the Pin Swizzle Map entry in a single line separated by semi-colons. 

BYTE_SWIZZLE_CH0=1,0,X,X,X,X,X,X;
PIN_SWIZZLE_CH0_DQS1=9,11,8,10,13,15,14,12;
PIN_SWIZZLE_CH0_DQS0=6,7,4,5,0,3,2,1;
BYTE_SWIZZLE_CH1=X,X,X,X,X,X,1,0;
PIN_SWIZZLE_CH1_DQS1=15,8,10,9,11,13,12,14;
PIN_SWIZZLE_CH1_DQS0=7,6,4,5,3,2,1,0;

Pin Swizzle Map for DIMM interface

For DIMM topologies, you must incorporate the component-to-module DQ map (refer to the memory vendor's datasheet), to determine the pin swizzling specification for the DIMM interface.

Consider the example in the table below, which represents DQS group 0 for channel 0 on the DDR5 RDIMM interface on the Agilex™ 7 FPGA M-Series Development Kit with MTC10F1084S1RC56BG1 DDR5 RDIMM memory.

Table 236.  Example of Component-to-Module DQ Map to Pin Swizzle from FPGA Schematics Targeting DIMM-type Memory Interface
Information From Dev Kit Schematic Information from Memory Vendor Data Sheet (Component-to-Module DQ Map)
Lane Pin Pin Index Net Name in Schematic Component Ref Number Module DQ Component DQ
BL6 FV23 83 M_A_DQ5_T_DDR5_RD U4 5A 7
FU24 82 M_A_DQ6_T_DDR5_RD 6A 6
FY23 81 M_A_DQ7_T_DDR5_RD 7A 5
GA24 80 M_A_DQ4_T_DDR5_RD 4A 4
FU26 79 M_A_DQS5_C_DDR5_RD    
FV25 78 M_A_DQS5_T_DDR5_RD    
GA26 77 M_A_DQS0_C_DDR5_RD    
FY25 76 M_A_DQS0_T_DDR5_RD    
FV27 75 M_A_DQ1_T_DDR5_RD 1A 1
FU28 74 M_A_DQ2_T_DDR5_RD 2A 0
FY27 73 M_A_DQ3_T_DDR5_RD 3A 3
GA28 72 M_A_DQ0_T_DDR5_RD 0A 2

For this specific group, the correct pin swizzling specification is:

PIN_SWIZZLE_CH0_DQS0 = 2,3,0,1,4,5,6,7;

(Note that the PIN_SWIZZLE_CH0_DQS0 = 0,3,2,1,4,7,6,5; specification would be incorrect. Pin swizzling specifications can be different when using different DIMMs.)

The example below shows the full Pin Swizzle Map parameters based on an Agilex™ 7 M-Series development kit targeting an MTC10F1084S1RC56BG1 DDR5 RDIMM memory interface. All parameters must be added in the Pin Swizzle Map entry in a single line separated by semi-colons. Ensure that the DQ pin swizzles are based on the component DQ index and not the Module/DIMM DQ index; inaccurate swizzling will result in calibration failure. 

BYTE_SWIZZLE_CH0=X,ECC,2,1,X,X,0,3;
PIN_SWIZZLE_CH0_DQS0=2,3,0,1,4,5,6,7;
PIN_SWIZZLE_CH0_DQS1=8,11,10,9,13,15,12,14;
PIN_SWIZZLE_CH0_DQS2=18,17,16,19,20,23,21,22;
PIN_SWIZZLE_CH0_DQS3=27,24,25,26,29,30,28,31;
PIN_SWIZZLE_CH0_ECC=2,1,0,3,4,7,6,5; 
BYTE_SWIZZLE_CH1=0,1,X,X,3,2,ECC,X;
PIN_SWIZZLE_CH1_DQS0=0,1,3,2,4,5,7,6;
PIN_SWIZZLE_CH1_DQS1=8,10,9,11,12,13,15,14;
PIN_SWIZZLE_CH1_DQS2=19,16,18,17,21,22,23,20;
PIN_SWIZZLE_CH1_DQS3=25,26,24,27,31,28,30,29;
PIN_SWIZZLE_CH1_ECC=6,5,7,4,0,3,2,1;
Level Two Title